MSP430F423AIPM datasheet(19/45 Pages) TI

19 / 45 page

MSP430F42xA

MIXED SIGNAL MICROCONTROLLER

SLAS587 -- FEBRUARY 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

Schmitt-trigger inputs -- Ports P1 and P2, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)

PARAMETER

VCC

MIN

TYP

MAX

UNIT

VIT+

Positive-going input threshold voltage

1.5

1.98

VIT--

Negative-going input threshold voltage

0.9

1.3

Vhys

Input voltage hysteresis (VIT+ -- VIT--)

0.45

inputs Px.x, TAx

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

External interrupt timing

Port P1, P2: P1.x to P2.x,External trigger signal

1.5

cycle

t(int)

External interrupt timing

Port P1, P2: P1.x to P2.x, External trigger signal

for the interrupt flag, (see Note 1)

t(cap)

Timer_A, capture timing

TAx

f(TAext)

Timer_A clock frequency

externally applied to pin

TACLK, INCLK t(H) =t(L)

MHz

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

MHz

NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with

trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in

MCLK cycles.

leakage current (see Note 1)

PARAMETER

TEST CONDITIONS

VCC

MIN

NOM

MAX

UNIT

Ilkg(P1.x)

Leakage

Port P1 Port 1: V(P1.x) (see Note 2)

3 V

±50

Ilkg(P2.x)

Leakage

current

Port P2 Port 2: V(P2.x) (see Note 2)

3 V

±50

NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

2. The port pin must be selected as an input.

outputs -- Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

High level output voltage

IOH(max) = --1.5mA(seeNote1)

3 V

VCC--0.25

VCC

VOH

High-level output voltage

IOH(max) = --6mA(seeNote2)

3 V

VCC--0.6

VCC

Low level output voltage

IOL(max) = 1.5mA(seeNote1)

3 V

VSS

VSS+0.25

VOL

Low-level output voltage

IOL(max) = 6mA(seeNote2)

3 V

VSS

VSS+0.6

NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the

maximum specified voltage drop.

2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the

maximum specified voltage drop.

output frequency

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

fPx.y

(1 ≤ x ≤ 2, 0 ≤ y ≤ 7)

CL =20pF, IL = ± 1.5 mA

MHz

fACLK,

fMCLK,

fSMCLK

P1.1/TA0/MCLK

P1.5/TACLK/ACLK/S28

CL =20pF

MHz

P1 5/TACLK/ACLK/S28

fACLK =fLFXT1 =fXT1

40%

60%

Duty cycle of output

P1.5/TACLK/ACLK/S28,

CL = 20 pF

fACLK =fLFXT1 =fLF

30%

70%

tXdc

Duty cycle of output

frequency

CL = 20 pF

fACLK =fLFXT1

50%

Xdc

frequency

P1.1/TA0/MCLK, CL =20pF, fMCLK =fDCOCLK

50%--

15 ns

50%

50%+

15 ns

MSP430F423AIPM Datasheet(PDF) 19 Page - Texas Instruments

MSP430F423AIPM Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL