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STP1612PW05 Datasheet(PDF) 12 Page - STMicroelectronics |
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STP1612PW05 Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 35 page ![]() Electrical characteristics STP1612PW05 12/35 Doc ID 15819 Rev 4 Figure 4. Test circuit for switching characteristics Table 11. Switching characteristics (VDD = 3.3 V) Symbol Characteristics Conditions Min. Typ. Max. Unit tSU0 Setup time SDI - DCLK ↑ VDD = 3.3 V VIH = VDD VIL = GND Rext = 460 Ω VLED = 4.5 V RL = 152 Ω CL = 10 pF C1 = 100 nF C2 = 10 μF 1 ns tSU1 LE ↑ – DCLK ↑ 1 ns tSU2 LE ↓ – DCLK ↑ 5 ns tH0 Hold time CLK ↑ - SDI 3 ns tH1 CLK ↑ - LE ↓ 7 ns tPD0 Propagation delay time CLK - SDO 45 40 ns tPD1 PWCLK-OUTn4(1) 1. Refer to the timing waveform Figure 4, where n = 0, 1, 2, 3. 120 ns tPD2 LE – SDO(2) 2. In timing of “read configuration” and “read error status code”, the next CLK rising edge should be tPD2 after the falling edge of LE. 45 40 ns tDL1 Stagger delay time OUTn4 + 1 (1) 40 ns tDL2 OUTn4 + 2 (1) 80 ns tDL3 OUTn4 +3 (1) 120 ns tw(L) Pulse width LE 5 ns tw(CLK) CLK 20 ns tw(PWCLK) PWCLK 20 ns tON Output rise time of output ports 11.6 ns tOFF Output fall time of output ports 7 ns tDEC Error detection duration 0.5 1 μs P W CLK CLK LE DD V EXT - R GND SDO OUT0 . .. Generator Function DD I OUT I C L V LED waveform input Logic SDI OUT 15 1 C 2 C V IH,VIL V IH=VDD VIL=GND R ext R L R L C L C L V DD |
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