STP1612PW05 datasheet(17/35 Pages) STMICROELECTRONICS

17 / 35 page

STP1612PW05

Grey scales data loading

Doc ID 15819 Rev 4

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Grey scales data loading

The STP1612PW05 is able to manage a gray-scale depth of 12 or 16 bits for each output,

exploiting an e-PWM algorithm.

The bit D of the configuration register is used to select the grey-scale loading. Its value can

be set to “0” for 12 bits or “1” for 16 bits. By default, D is set to “0”.

Loading of the data is performed through the serial input on a dedicated buffer and two

different methods can be used.

With both methods, the first incoming data packet is relative to the output 15; the following

packet is relative to the output 14 and so on up to the output 0.

If F=”0”, when a data packet has been loaded, the latch signal (LE) must become active for

one CLK cycle (data latch). When the last data packet, relative to the output 0, has been

loaded, the latch signal must be active for two CLK cycles (global latch) and all the data will

be transferred to the e-PWM registers starting from the MSB.

If F=”1” all data packets (12 or 16 bits x16) are loaded and then the global latch signal must

be active and all the data will be transferred to the e-PWM registers starting from the MSB.

Figure 7.

Full timing for data loading

STP1612PW05 Datasheet(PDF) 17 Page - STMicroelectronics