LPC4350 datasheet(6/145 Pages) NXP

Part #	LPC4350

Description	32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet two High-speed USBs; advanced configurable peripherals

PDF	145 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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6 / 145 page

LPC4350_30_20_10

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Objective data sheet

Rev. 2.1 — 23 September 2011

6 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

Block diagram

(1) Not available on all parts (see Table 2).

Fig 1.

LPC4350/30/20/10 Block diagram

ARM

CORTEX-M4

TEST/DEBUG

INTERFACE

GPDMA

LCD(1)

SD/

MMC

ETHERNET(1)

10/100

MAC

IEEE 1588

HIGH-SPEED

USB0(1)

HOST/

DEVICE/OTG

HIGH-SPEED

USB1(1)

HOST/DEVICE

EMC

HIGH-SPEED PHY

32 kB AHB SRAM

16 +16 kB AHB SRAM

SPIFI

AES

HS GPIO

SPI

SGPIO

SCT

64 kB ROM

I2C0

I2S0

I2S1

C_CAN1

MOTOR

CONTROL

PWM(1)

TIMER3

TIMER2

USART2

USART3

SSP1

RI TIMER

QEI(1)

GIMA

BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

AHB MULTILAYER MATRIX

LPC4350/30/20/10

128 kB LOCAL SRAM

72 kB LOCAL SRAM

10-bit ADC0

10-bit ADC1

C_CAN0

I2C1

10-bit DAC

BRIDGE

RGU

CCU2

CGU

CCU1

ALARM TIMER

CONFIGURATION

REGISTERS

OTP MEMORY

EVENT ROUTER

POWER MODE CONTROL

12 MHz IRC

RTC POWER DOMAIN

BACKUP REGISTERS

RTC OSC

RTC

002aaf772

slaves

masters

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

= connected to GPDMA

GPIO

INTERRUPTS

GPIO GROUP0

INTERRUPT

GPIO GROUP1

INTERRUPT

WWDT

USART0

UART1

SSP0

TIMER0

TIMER1

SCU

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