LPC4350 datasheet(74/145 Pages) NXP

74 / 145 page

LPC4350_30_20_10

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Objective data sheet

Rev. 2.1 — 23 September 2011

74 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

7.16.2 Serial GPIO (SGPIO)

The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate

serial stream processing.

7.16.2.1

Features

• Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to

serial data conversion.

• 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value

from a pin or an output value to a pin with every cycle of a shift clock.

• Each slice is double-buffered.

• Interrupt is generated on a full FIFO, shift clock, or pattern match.

• Slices can be concatenated to increase buffer size.

• Each slice has a 32-bit pattern match filter.

7.17 AHB peripherals

7.17.1 General Purpose DMA (GPDMA)

The DMA controller allows peripheral-to memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receives. The

source and destination areas can each be either a memory region or a peripheral for

master 1, but only memory for master 0.

7.17.1.1

Features

• Eight DMA channels. Each channel can support an unidirectional transfer.

• 16 DMA request lines.

• Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers are supported.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority.

• AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

• Two AHB bus masters for transferring data. These interfaces transfer data when a

DMA request goes active. Master 1 can access memories and peripherals, master 0

can access memories only.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

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