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LPC4350 Datasheet(PDF) 109 Page - NXP Semiconductors |
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LPC4350 Datasheet(HTML) 109 Page - NXP Semiconductors |
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109 / 145 page ![]() LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2.1 — 23 September 2011 109 of 145 NXP Semiconductors LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller Fig 29. SSP master timing in SPI mode SCK (CPOL = 0) MOSI MISO Tcy(clk) tclk(H) tclk(L) tDS tDH tv(Q) DATA VALID DATA VALID th(Q) SCK (CPOL = 1) DATA VALID DATA VALID MOSI MISO tDS tDH DATA VALID DATA VALID th(Q) DATA VALID DATA VALID tv(Q) CPHA = 1 CPHA = 0 002aae829 |
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