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LPC4350 Datasheet(PDF) 114 Page - NXP Semiconductors |
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LPC4350 Datasheet(HTML) 114 Page - NXP Semiconductors |
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114 / 145 page ![]() LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2.1 — 23 September 2011 114 of 145 NXP Semiconductors LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller Fig 34. External static memory read/write access (PB = 1) RD1 WR1 EMC_Ax WR8 WR4 WR8 EMC_CSx RD2 RD7 RD7 RD4 EMC_OE EMC_BLSx EMC_WE RD5 WR6 WR2 RD5 RD5 RD5 RD6 RD3 EOR EOW EMC_Dx WR3 WR5 WR7 002aag215 Fig 35. External static memory burst read cycle RD5 RD5 RD5 RD5 EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE EMC_Dx 002aag216 Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 CL =30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>. Symbol Parameter Conditions Min Typ Max Unit Common to read and write cycles Tcy(clk) clock cycle time <tbd> - - ns td(SV) chip select valid delay time <tbd> <tbd> <tbd> ns th(S) chip select hold time <tbd> <tbd> <tbd> ns td(RASV) row address strobe valid delay time <tbd> <tbd> <tbd> ns th(RAS) row address strobe hold time <tbd> <tbd> <tbd> ns td(CASV) column address strobe valid delay time <tbd> <tbd> <tbd> ns th(CAS) column address strobe hold time <tbd> <tbd> <tbd> ns |
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