LS013B4DN02 datasheet(17/29 Pages) SHARP

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SPEC No.

LCY-12T09303B

MODEL No.

LS013B4DN02

PAGE

6-5-2 Data Update Mode (Multiple Lines)

Updates arbitrary multiple lines data. (M0=”H”、M2＝”L”)

SCS

DUMMY DATA(don't care)

SCLK

DUMMY DATA(don't care)

D95

DMY

AG6

AG5

AG4

AG0

AG1

D96

AG3

DMY

AG6

AG5

AG4

D94

D95

DMY

AG6

AG5

DMY

AG1

AG0

D93

D96

DMY

D95

D96

D94

AG0

AG1

AG2

tsSI

thSI

tsSCS

GL1

Data transfer period

(96ck)

GL2

Mode selection period

(3ck+5ckDMY)

GL(n)th line

Data writing period

(96ck)

Data transfer period

(16ck)

GL(n-1)th Line

thSCS

twSCLKH

twSCLKL

twSCSL

twSCSH

Gate line address period

(7ck+1ckDMY)

Data transfer period

(8ck(Dymmy)+7ck(address)+1ck(Dummy)=16ck)

Data transfer period

(8ck(Dummy)+7ck(address)+1ck(Dummy)=16ck)

M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)

When “L”, display mode (maintain memory internal data).

M1: Frame inversion flag.

When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.

When EXTMODE=”H”, it can be “H” or “L”.

M2: All clear flag.

Refer to 6-5-4) All Clear Mode to execute clear.

DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)

※

Data write period

Data is being stored in 1

st latch block of binary driver on panel.

※

Data transfer period

For example, during GL2nd line data transfer period, GL 2

nd line address is latched and GL1st

line data is transferred from 1

st latch to pixel internal memory circuit at the same time.

※

For gate line address setting, refer to 6-6) Input Signal and Display.

※

Input data continuously.

※

M1: Frame inversion flag is enabled when EXTMODE= L .

※

When SCS becomes L , M0 and M2 are cleared.

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