DS89C430 datasheet(26/46 Pages) DALLAS

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DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers

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External Memory

The DS89C430 executes external memory cycles for code fetches and read/writes of external program and data

memory. A nonpage external memory cycle is four times slower than the internal memory cycles (i.e., an external

memory cycle contains four system clocks). However, a page mode external memory cycle can be completed in

one, two, or four system clocks for a page hit and two, four, or eight system clocks for a page miss, depending on

user selection. The DS89C430 also supports a second page mode operation with a different external bus structure

that provides for fast external code fetches but uses four system clock cycles for data memory access.

External Program Memory Interface (Nonpage Mode)

Figure 7 shows the timing relationship for internal and external code fetches when CD1 and CD0 are set to 10b,

assuming the microcontroller is in nonpage mode for external fetches. Note that an external program fetch takes

four system clocks, and an internal program fetch requires only one system clock.

As illustrated in Figure 7, ALE is deasserted when executing an internal memory fetch. The DS89C430 provides a

programmable user option to turn on ALE during internal program memory operation. ALE is automatically enabled

for code fetch externally, independent of the setting of this option.

PSEN is only asserted for external code fetches, and is inactive during internal execution.

Figure 7. External Program Memory Access (Nonpage Mode, CD1:CD0 = 10)

Internal Memory Cycles

XTAL1

ALE

Port 0

Port 2

PSEN

External Memory Cycle

MSB Add

LSB Add

Data

LSB Add

Data

DS89C430 Datasheet(PDF) 26 Page - Dallas Semiconductor