TJ2997GD datasheet(5/13 Pages) HTC

5 / 13 page

DDR Termination Regulator

TJ2997

Apr, 2011 - R1.0.1

5/13

HTC

DESCRIPTION

The TJ2997 is a linear bus termination regulator designed for DDR II and DDR III memories. The

output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2.

The output stage has been designed to maintain excellent load regulation while preventing shoot through.

The TJ2997 also incorporates two distinct power rails that separate the analog circuitry from the power

output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It

also permits the TJ2997 to provide a termination solution for the next generation of DDR-SDRAM

memory..

Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission

across the memory bus.

This termination scheme is essential to prevent data error from signal

reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common

form of termination is Class II single parallel termination. This involves one RS series resistor from the

chipset to the memory and one RT termination resistor. Typical values for RS and RT are 25 Ohms,

although these can be changed to scale the current requirements from the TJ2997. This implementation

can be seen below in Figure 1.

FIGURE 1. SSTL-Termination Scheme

PIN DESCRIPTION

AVIN AND PVIN

AVIN and PVIN are the input supply pins for the TJ2997. AVIN is used to supply all the internal control

circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to

create VTT. These pins have the capability to work off separate supplies depending on the application.

Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON

limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power

loss will also increase, thermally limiting the design.

The limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is

recommended to connect PVIN to voltage rails equal to or less than 3.3V to prevent the thermal limit from

tripping because of excessive internal power dissipation.

If the junction temperature exceeds the

thermal shutdown then the part will enter a shutdown state where both VTT and VREF are tri-stated.

VDDQ

VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference

voltage is generated from a resistor divider of two internal 50kΩ resistors. This guarantees that VTT will

track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be

TJ2997GD Datasheet(PDF) 5 Page - HTC Korea TAEJIN Technology Co.