HT82V42 datasheet(8/24 Pages) HOLTEK

8 / 24 page

HT82V42

Rev. 1.20

December 8, 2010

System Architecture

Introduction

A device block diagram showing the signal paths pres-

ent is provided. The HT82V42 samples a single channel

input VIN. The device then processes the sampled video

signal with respect to the video reset level or an inter-

nally/externally generated reference level for signal pro-

cessing. The processing channel consists of an Input

Sampling block with optional Reset Level Clamping

(RLC) and Correlated Double Sampling (CDS), an 8-bit

programmable offset DAC and an 8-bit Programmable

Gain Amplifier (PGA). The ADC then converts this ana-

logue signal to a 16-bit digital word. The digital output

from the ADC is presented on a 4-bit wide bus. On-chip

control registers determine the configuration of the de-

vice, including the offsets and gains applied to R/G/B

signal. These registers are programmable via a serial

interface.

Input Sampling

The HT82V42 can sample and process the input ana-

logue signals as follows:

· Monochrome

A single chosen input VIN is sampled, processed by

the corresponding channel, and converted by the

ADC. The choice of input can be changed via the con-

trol interface, e.g. on a line-by-line basis if required.

· Colour Line-by-Line

A single chosen input (Red, Green and Blue) is sam-

pled and multiplexed into the analogue channel for

processing before being converted by the ADC. The

input selected can be switched in turn (Red

® Green

® Blue ® Red ¼) together with the PGA and Offset

DAC control registers by pulsing the RLC/ACYC pin.

This is known as auto-cycling. Alternatively, other

sampling sequences can be generated via the control

registers. Refer to the Line-by-Line Operation section

for more details.

Clamp Voltage

The device contains an integrated single 4-bit DAC

which is controlled by register setting for the clamp volt-

age. The internal clamp is sampled on the positive edge

of DCLK that occurs during each CDSCLK2 pulse. The

sampled level, high (or low) controls the presence (or

absence) of the internal CL pulse on the next reset level.

The position of CL can be adjusted by using control bits

CDSREF[1:0].

Reset Sample and Clamp Timing

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