HT82V42 datasheet(17/24 Pages) HOLTEK

17 / 24 page

HT82V42

Rev. 1.20

December 8, 2010

· Register Map Description

Bit

No.

Bit Name

POR

Description

Setup Register 1

0EN

0: Complete power down

1: fully active

CDS

Select correlated double sampling mode.

0: non-CDS mode

1: CDS mode

Reserved

Default 1

Reserved

Default 1

5~4

PGAFS[1:0]

Adjust PGA output to optimize the ADC range for different po-

larity sensor output signals. Zero differential PGA input signal

gives.

00: Zero output (use for bipolar video)

01: Zero output

10: Full-scale positive output (use for negative going video)

11: Full-scale negative output (use for positive going video)

Mode3

Mode3 setting

1: Mode3 enable

Setup Register 2

INVOP

Digitally inverts the polarity of output data

0: negative going video gives negative going output

1: negative going video gives positive going output

VRLCEXT

Setting this bit high, changes VRLC/VBIAS to Hi-Z, allowing

VRLC/VBIAS to be driven from an external power source.

RLCDACRN

Sets the output range of the RLCDAC.

0: RLCDAC ranges from 0 to AVDD.

1: RLCDAC ranges from 0 to VRT

7~6

DEL[1:0]

Sets the output latency for the ADC clock periods.

1 ADC clock=2 DCLK periods. Under mode3, 1 ADC clock=3

DCLK periods.

00: Minimum latency

01: Delay by 1 ADC clock

10: Delay by 2 ADC clock

11: Delay by 3 ADC clock

Setup Register 3

3~0

RLVC[3:0]

1111

Controls RLCDAC driving The VRLC pin defines the single

ended signal reference voltage or Reset Level Clamp Volt-

age. Refer to the Electrical Characteristic section for details.

CDSREF[1:0]

Adjust reset timing under CDS mode

00: Advance 1 DCLK period

01: Normal

10: Retard 1 DCLK

11: Retard 2 DCLK

7~6

Reserved

Software Reset

Any write to this register will cause all functions to be reset. It

is recommended to execute a software reset after each power

on reset and before any other register writes. When this regis-

ter is written, the reset function will be initiated immediately by

an internal reset signal. If the DCLK exists, the internal reset

signal will keep active for about 2 DCLK cycles. Otherwise,

the device will keep in reset state all the time.

HT82V42 Datasheet(PDF) 17 Page - Holtek Semiconductor Inc

HT82V42 Datasheet(HTML) 17 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL