HT82V42 datasheet(12/24 Pages) HOLTEK

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HT82V42

Rev. 1.20

December 8, 2010

Control Interface

The internal control registers are programmed via the

serial digital control interface. The register contents can

be read back via the serial interface on pin OD3/SDO. It

is recommended that a software reset is carried out after

the power-up sequence, before writing to any other reg-

ister. This ensures that all registers are set to their de-

fault values

Serial Interface

- Register Write

Figure shows the register writing in serial mode. Three

pins, SCK, SDI and SEN are used. A six-bit address (a5,

a4, a3, a2, a1, a0) is clocked in through SDI, MSB first,

followed by an eight-bit data word (b7, b6, b5, b4, b3,

b2, b1, b0), also MSB first. Each bit is latched on the ris-

ing edge of SCK. When the data has been shifted into

the device, a pulse is applied to SEN to transfer the data

to the appropriate internal register. Note all valid regis-

ters have address bit a4 equal to 0 in the write mode.

A software reset is carried out by writing to Address

²000100² with any value of data, i.e. Data Word =

XXXXXXXX.

Serial Interface

- Register Read-back

Figure shows register read-back in serial mode.

Read-back is initiated by writing to the serial bus as de-

scribed above but with address bit a4 set to 1, followed

by an 8-bit dummy data word. Writing address (a5, 1,

a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4,

d3, d2, d1, d0) of the corresponding register (a5, 0, a3,

a2, a1, a0) to be output MSB first on pin SDO (on the

falling edge of SCK). Note that pin SDO is shared with

an output pin, OD3. It must be noted that when reading

from a register the OD3 pin function will be disabled and

cannot be read by the external MCU. The next word

may be read in to SDI while the previous word is still be-

ing output on SDO.

Timing Requirement

To use this device a master clock (DCLK) of up to

30MHz and a per-pixel synchronisation clock

(CDSCLK2) of up to 15MHz are required. These clocks

drive a timing control block, which produces internal sig-

nals to control the sampling of the video signal. The

DCLK to CDSCLK2 ratios and maximum sample rates

for the various modes are shown in Table.

Programmable CDSCLK2 Detect Circuit

The CDSCLK2 input is used to determine the sampling

point and frequency of the HT82V42. Under normal op-

eration a pulse of 1 DCLK period should be applied to

CDSCLK2 at the desired sampling frequency (as shown

in the Operating Mode Timing Diagrams) and the input

sample will be taken on the first rising DCLK edge after

CSDCLK2 has gone low. However, in certain applica-

tions such a signal may not be readily available. The

programmable CDSCLK2 detect circuit in the HT82V42

allows the sampling point to be derived from any signal

of the correct frequency, such as a CCD shift register

clock, when applied to the CDSCLK2 pin. When en-

abled, by setting the VSMPDET control bit, the circuit

detects either a rising or falling edge (determined by the

POSNNEG control bit) on the CDSCLK2 input pin and

generates an internal VSMP pulse. This pulse can op-

tionally be delayed by a number of DCLK periods, speci-

fied by the VDEL[2:0] bits. Figure shows the internal

VSMP pulses that can be generated by this circuit for a

typical clock input signal. The internal VSMP pulse is

then applied to the timing control block in place of the

normal CDSCLK2 pulse provided from the input pin.

The sampling point then occurs on the first rising DCLK

edge after this internal VSMP pulse, as shown in the Op-

erating Mode Timing Diagrams.

Serial Interface Register Write

Serial Interface Register Read-back

HT82V42 Datasheet(PDF) 12 Page - Holtek Semiconductor Inc

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