PIC24F08KL402 datasheet(33/260 Pages) MICROCHIP

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PIC24F16KL402 FAMILY

DS31037B-page 33

 2011 Microchip Technology Inc.

4.2

Data Address Space

The PIC24F core has a separate, 16-bit wide data

memory space, addressable as a single linear range.

The data space is accessed using two Address

Generation Units (AGUs); one each for read and write

operations. The data space memory map is shown in

Figure 4-3.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This gives a data space address range of 64 Kbytes or

32K words. The lower half of the data memory space

(that is, when EA<15> = 0) is used for implemented

memory addresses, while the upper half (EA<15> = 1) is

reserved for the Program Space Visibility (PSV) area

(see Section 4.3.3 “Reading Data From Program

Memory Using Program Space Visibility”

Depending on the particular device, PIC24F16KL402

family devices implement either 512 or 1024 words of

data memory. If an EA points to a location outside of

this area, an all zero word or byte will be returned.

4.2.1

DATA SPACE WIDTH

The

data

memory

space

organized

byte-addressable, 16-bit wide blocks. Data is aligned in

data memory and registers as 16-bit words, but all the

data space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

FIGURE 4-3:

DATA SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES(3)

0000h

07FEh

FFFEh

LSB

Address

LSB

MSB

Address

0001h

07FFh

0BFFh(2)

FFFFh

8001h

8000h

7FFFh

0801h

0800h

Near

0BFEh(2)

SFR

SFR Space

Data RAM

7FFFh

Program Space

Visibility Area

Note 1:

Upper data memory boundary for PIC24FXXKL10X/20X devices.

Upper data memory boundary for PIC24FXXKL30X/40X devices.

Data memory areas are not shown to scale.

1FFEh

1FFFh

Space

Data Space

Implemented

Data RAM

Unimplemented

Read as ‘0’

09FFh(1)

09FEh(1)

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