RL78 datasheet(70/100 Pages) RENESAS

Part #	RL78

Description	True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC LVD), 1.6 V to 5.5 V operation

PDF	100 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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70 / 100 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS

R01DS0053EJ0100 Rev. 1.00

Page 70 of 97

Feb 21, 2012

Caution

The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.

Simplified I2C mode mode connection diagram (during communication at same potential)

Simplified I2C mode serial transfer timing (during communication at same potential)

Caution

Select the TTL input buffer and the N-ch open drain output (EVDD0 tolerance) mode for the SDAr pin and the N-ch

open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port

output mode register h (POMh).

Remark 1. Rb[

]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance

Remark 2.

r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 3 to 5, 14),

h: POM number (h = 0, 1, 3 to 5, 7, 14)

Remark 3.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),

n: Channel number (n = 0, 2), mn = 00 to 03, 10 to 13)

SDAr

SCLr

User’s device

SDA

SCL

VDD

RL78/G14

SDAr

SCLr

1/fSCL

tLOW

tHIGH

tSU: DAT

tHD: DAT

RL78 Datasheet(PDF) 70 Page - Renesas Technology Corp