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AD9737ABBCZ Datasheet(PDF) 43 Page - Analog Devices |
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AD9737ABBCZ Datasheet(HTML) 43 Page - Analog Devices |
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43 / 64 page ![]() Data Sheet AD9737A/AD9739A Rev. | Page 43 of 64 Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default CROSS_ CNT2 0x23 N/A N/A N/A DIR_N CLKN_ OFFSET[3] CLKN_ OFFSET[2] CLKN_ OFFSET[1] CLKN_ OFFSET[0] 0x00 PHS_DET 0x24 N/A N/A CMP_BST PHS_DET AUTO_EN N/A N/A N/A N/A 0x00 MU_DUTY 0x25 MU_ DUTYAUTO_ EN POS/NEG ADJ[5] ADJ[4] N/A N/A N/A N/A 0x00 MU_CNT1 0x26 N/A Slope Mode[1] Mode[0] Read Gain[1] Gain[0] Enable 0x42 MU_CNT2 0x27 MUDEL[0] SRCH_ MODE[1] SRCH_ MODE[0] SET_PHS[4] SET_PHS[3] SET_PHS[2] SET_PHS[1] SET_PHS[0] 0x40 MU_CNT3 0x28 MUDEL[8] MUDEL[7] MUDEL[6] MUDEL[5] MUDEL[4] MUDEL[3] MUDEL[2] MUDEL[1] 0x00 MU_CNT4 0x29 SEARCH_TOL Retry CONTRST Guard[4] Guard[3] Guard[2] Guard[1] Guard[0] 0x0B MU_STAT1 0x2A N/A N/A N/A N/A N/A N/A MU_LOST MU_LKD 0x00 RSVD 0x2B N/A N/A N/A N/A N/A N/A N/A N/A N/A RSVD 0x2C N/A N/A N/A N/A N/A N/A N/A N/A N/A ANA_CNT1 0x32 N/A N/A N/A N/A N/A N/A N/A N/A 0xCA ANA_CNT2 0x33 N/A N/A N/A N/A N/A N/A N/A N/A 0x03 RSVD 0x34 N/A N/A N/A N/A N/A N/A N/A N/A N/A PART_ID 0x35 ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] 0x40 SPI PORT CONFIGURATION AND SOFTWARE RESET Table 11. SPI Port Configuration and Software Reset Register (Mode) Address (Hex) Bit Name Bits R/W Default Setting Description 0x00 SDIO_DIR 7 R/W 0x0 0 = 4-wire SPI, 1 = 3-wire SPI. LSB/MSB 6 R/W 0x0 0 = MSB first, 1 = LSB first. Reset 5 R/W 0x0 Software reset is recommended before modification of other SPI registers from the default setting. 0 = inactive state; allows the user to modify registers from the default setting. 1 = causes all registers (except 0x00) to be set to the default setting. POWER-DOWN LVDS INTERFACE AND TxDAC® Table 12. Power-Down LVDS Interface and TxDAC Register (Power-Down) Address (Hex) Bit Name Bits R/W Default Setting Description 0x01 LVDS_DRVR_PD 5 R/W 0x0 Power-down of the LVDS drivers/receivers and TxDAC. 0 = enable, 1 = disable. LVDS_RCVR_PD 4 R/W 0x0 CLK_RCVR_PD 1 R/W 0x0 DAC_BIAS_PD 0 R/W 0x0 CONTROLLER CLOCK DISABLE Table 13. Controller Clock Disable Register (CNT_CLK_DIS) Address (Hex) Bit Name Bits R/W Default Setting Description 0x02 CLKGEN_PD 3 R/W 0x0 Internal CLK distribution enable: 0 = enable, 1 = disable. REC_CNT_CLK 1 R/W 0x1 LVDS receiver and Mu controller clock disable. 0 = disable, 1 = enable. MU_CNT_CLK 0 R/W 0x1 C |
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