AD9737ABBCZ datasheet(61/64 Pages) AD

61 / 64 page

Data Sheet

AD9737A/AD9739A

Rev. | Page 61 of 64

LAB EVALUATION OF THE AD9737A/AD9739A

Figure 187 shows a recommended lab setup that was used to

characterize the performance of the AD9737A/AD9739A. The

DPG2 is a dual port LVDS/CMOS data pattern generator that is

available from Analog Devices, Inc., with an up to 1.25 GSPS

data rate. The DPG2 directly interfaces to the AD9737A/AD9739A

evaluation board via Tyco Z-PACK HM-Zd connectors. A low

phase noise/jitter RF source such as an R&S SMA100A signal

generator is used for the DAC clock. A +5 V power supply is

used to power up the AD9737A/AD9739A evaluation board,

and SMA cabling is used to interface to the supply, clock source,

and spectrum analyzer. A USB 2.0 interface to a host PC is used

to communicate to both the AD9737A/AD9739A evaluation

board and the DPG2.

A high dynamic range spectrum analyzer is required to evaluate

the ac performance of the AD9737A/AD9739A reconstructed

waveform. This is especially the case when measuring ACLR

performance for high dynamic range applications such as

multicarrier DOCSIS CMTS applications. Harmonic, SFDR,

and IMD measurements pertaining to unmodulated carriers

can benefit by using a sufficiently high RF attenuation setting

because these artifacts are easy to identify above the spectrum

analyzer noise floor. However, reconstructed waveforms having

modulated carrier(s) often benefit from the use of a high dynamic

range RF amplifier and/or passive filters to measure close-in

and wideband ACLR performance when using spectrum

analyzers of limited dynamic range.

ADI PATTERN GENERATOR

DPG2

AD9739

EVAL. BOARD

RHODE AND

SCHWARTZ

SMA 100A

AGILENT PSA

E4440A

10 MHz

REFIN

10 MHz

REOUT

LAB

USB 2.0

GPIB

LVDS

DATA

AND DCI

DCO

1.6GHz TO

2.5GHz

3dBm

POWER

SUPPLY

+5V

Figure 187. Lab Test Setup Used to Characterize the AD9737A/AD9739A

RECOMMENDED START-UP SEQUENCE

On power-up of the AD9737A/AD9739A, a host processor is

required to initialize and configure the AD9737A/AD9739A

via its SPI port. Figure 188 shows a flowchart of the sequential

steps required. Table 29 provides more detail on the SPI register

write/read operations required to implement the flowchart

steps. Note the following:

•

A software reset is optional because the AD9737A/AD9739A

have both an internal POR circuit and a RESET pin.

•

The Mu controller must be first enabled (and in track mode)

before the data receiver controller is enabled because the DCO

output signal is derived from this circuitry.

•

A wait period is related to fDATA periods.

•

Limit the number of attempts to lock the controllers to three;

locks typically occur on the first attempt.

•

Hardware or software interrupts can be used to monitor the

status of the controllers.

CONFIGURE

SPI PORT

SOFTWARE

RESET

SET CLK

INPUT CMV

CONFIGURE

MU CONT.

WAIT A

FEW 100µs

MU CONT.

LOCKED?

YES

WAIT A

FEW 100µs

RECONFIGURE

TXDAC FROM

DEFAULT SETTING

OPTIONAL

CONFIGURE

RX DATA

CONT.

RX DATA

CONT.

LOCKED?

Figure 188. Flowchart for Initialization and Configuration of the

AD9737A/AD9739A

AD9737ABBCZ Datasheet(PDF) 61 Page - Analog Devices

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