ADE7880 datasheet(7/104 Pages) AD

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Data Sheet

ADE7880

Rev. A | Page 7 of 104

Parameter1, 2

Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLY

For specified performance

PSM0 Mode

VDD Pin

2.97

3.63

Minimum = 3.3 V − 10%; maximum =

3.3 V + 10%

IDD

PSM1 and PSM2 Modes

VDD Pin

2.4

3.7

IDD

PSM1 Mode

5.3

5.8

PSM2 Mode

0.2

0.27

PSM3 Mode

For specified performance

VDD Pin

2.4

3.7

IDD in PSM3 Mode

1.8

μA

1 See the Typical Performance Characteristics section.

2 See the Terminology section for a definition of the parameters.

⎥

⎦

⎤

⎢

⎣

⎡

2800

means the whole number of the division.

4 The CLKIN/CLKOUT load capacitors refer to the capacitors that are mounted between the CLKIN and CLKOUT pins of the ADE7880 and AGND. The capacitors should

be chosen based on the crystal manufacturer’s data sheet specification, and they must not have more than the maximum value specified in the table.

TIMING CHARACTERISTICS

VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Note that dual

function pin names are referenced by the relevant function only within the timing tables and diagrams (see the Pin Configuration and

Function Descriptions section for full pin mnemonics and descriptions).

Table 2. I2C-Compatible Interface Timing Parameter

Standard Mode

Fast Mode

Parameter

Symbol

Min

Max

Min

Max

Unit

SCL Clock Frequency

fSCL

100

400

kHz

Hold Time (Repeated) Start Condition

tHD;STA

4.0

0.6

μs

Low Period of SCL Clock

tLOW

4.7

1.3

μs

High Period of SCL Clock

tHIGH

4.0

0.6

μs

Set-Up Time for Repeated Start Condition

tSU;STA

4.7

0.6

μs

Data Hold Time

tHD;DAT

3.45

0.9

μs

Data Setup Time

tSU;DAT

250

100

Rise Time of Both SDA and SCL Signals

1000

300

Fall Time of Both SDA and SCL Signals

300

Setup Time for Stop Condition

tSU;STO

4.0

0.6

μs

Bus Free Time Between a Stop and Start Condition

tBUF

4.7

1.3

μs

Pulse Width of Suppressed Spikes

tSP

N/A1

1 N/A means not applicable.

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