ADF4196BCPZ datasheet(19/28 Pages) AD

19 / 28 page

Data Sheet

ADF4196

Rev. B | Page 19 of 28

CHARGE PUMP REGISTER (R4) LATCH MAP

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C3 (1)

DB1

C2 (0)

DB0

C1 (0)

9-BIT TIMEOUT COUNTER

RESERVED

CONTROL

BITS

TIMER

SELECT

SW1/SW2

SW3

ICP

NOT USED

TIMER SELECT

..........

TIMEOUT COUNTER

508

509

510

511

xPFD CYCLES

2032

2036

2040

2044

DELAY µs1

0.15

0.30

0.46

78.15

78.30

78.46

78.61

1DELAY WITH 26MHz PFD

Figure 33. Bit Map for Register R4

R4, the charge pump register, is used for programming the timers

for loop filter switches. These switches help maintain the stability

of the loop filter after boosting the charge pump current.

Control Bits

to 1, 0, 0.

Reserved Bits

For normal operation, set the DB23 to DB14 reserved bits to

a hexadecimal code of 0x001.

9-Bit Timeout Counter

These bits are used to program the fast lock timeout counters.

The counters are clocked at one-quarter the PFD reference

frequency; therefore, their time delay scales with the PFD

frequency according to the following equation:

Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency)

For example, if 35 is loaded with timer select = 00, with

a 13 MHz PFD, SW1 and SW2 switch after the following:

(35 × 4)/13 MHz = 10.8 µs

Timer Select

The two timer select bits select the timeout counter that is to

be programmed. Note that setting up the ADF4196 for correct

operation requires setup of these three timeout counters: ICP,

SW1/SW2, and SW3. Therefore, three writes to this register

are required in the initialization sequence. Table 7 shows

example values for a GSM Tx synthesizer with a 60 kHz final

loop bandwidth. See the Applications Information section for

more information.

Table 7. Recommended Values for a GSM Tx LO

Timer

Select

Timeout

Counter

Value

Time (µs) with

PFD = 13 MHz

ICP

8.6

SW3

10.8

SW1/SW2

10.8

On each write to R0, the timeout counters start. Switch SW3 closes

until the SW3 counter times out. Similarly, the SW1 and SW2

switches close until the SW1/SW2 counter times out. When the

ICP counter times out, the charge pump current is ramped down

from 64× to 1× in six binary steps. It is recommended that the

SW1/SW2 and SW3 timeout counter values be set equal to the

ICP timeout counter value plus 7, as in the example shown in

Table 7.

ADF4196BCPZ Datasheet(PDF) 19 Page - Analog Devices

ADF4196BCPZ Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL