LT1640AL datasheet(22/36 Pages) LINER

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LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

425212fd

APPLICATIONS INFORMATION

At time point 8, the load current falls and the SENSE voltage

drops below VACL(t). The analog current limit loop shuts

off and the GATE pin ramps further. At time point 9, the

SENSE voltage drops below VCB, the fault TIMER cycle

ends, followed by a 5.8μA discharge cycle (cool off). The

duration between time points 7 and 9 must be shorter than

one circuit breaker delay to avoid a fault time out during

GATE ramp-up. When GATE ramps past the VGATEH thresh-

old at time point 10, PWRGD pulls low. At time point 11,

GATE reaches its maximum voltage as determined by VIN.

Live Insertion with Short Pin Control of UV/OV

In the example shown in Figure 10, power is delivered

through long connector pins whereas the UV/OV divider

makes contact through a short pin. This ensures the power

connections are firmly established before the LTC4252 is

activated. At time point 1, the power pins make contact

and VIN ramps through VLKO. At time point 2, the UV/OV

divider makes contact and its voltage exceeds VUVHI. In

addition, the internal logic checks for OV < VOVHI, GATE

< VGATEL, SENSE < VCB, SS < 20 • VOS and TIMER <

VTMRL. If all conditions are met, an initial timing cycle

starts and the TIMER capacitor is charged by a 5.8μA

current source pull-up. At time point 3, TIMER reaches the

VTMRH threshold and the initial timing cycle terminates.

The TIMER capacitor is quickly discharged. At time point

4, the VTMRL threshold is reached and the conditions of

GATE < VGATEL, SENSE < VCB and SS < 20 • VOS must be

GND – VEE OR

(–48RTN) – (–48V)

UV/OV

VIN

TIMER

GATE

VLKO

SENSE

VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB

OS AND TIMER < VTMRL

VOUT

3 4 56

VACL

VCB

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB

DRAIN

PWRGD

DRN

5.8μA

58μA

10 11

VIN – VGATEH

VDRNL

VDRNCL

CB + VOS)

ACL + VOS)

VGATEL

VTMRL

VTMRH

5.8μA

58μA

425212 F09

GATE

START-UP

INITIAL TIMING

Figure 9. System Power-Up Timing (All Waveforms Are Referenced to VEE)

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