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LTC4278

4278fc

between the primary-side switch and secondary-side syn-

chronous switch(es) and the subsequent current spike in

thetransformer.Thisspikewillcauseadditionalcomponent

stress and a loss in regulator efficiency.

The primary gate delay resistor is set with the following

equation:

RPGDLY kW

( )=

tPGDLY ns

( )+47

9.01

A good starting point is 15k.

Soft-Start Function

The LTC4278 contains an optional soft-start function that

is enabled by connecting an external capacitor between

the SFST pin and ground. Internal circuitry prevents the

control voltage at the VCMP pin from exceeding that on

the SFST pin. There is an initial pull-up circuit to quickly

bring the SFST voltage to approximately 0.8V. From there it

chargestoapproximately2.8Vwitha20µAcurrentsource.

The SFST node is discharged to 0.8V when a fault occurs.

A fault occurs when the current sense voltage is greater

than 200mV or the IC’s thermal (overtemperature) shut-

down is tripped. When SFST discharges, the VCMP node

voltage is also pulled low to below the minimum current

voltage. Once discharged and the fault removed, the

SFST charges up again. In this manner, switch currents

are reduced and the stresses in the converter are reduced

during fault conditions.

The time it takes to fully charge soft-start is:

tss =

CSFST •1.4V

µA

=70kW •CSFST µF

( )

Switcher’s UVLO Pin Function

The UVLO pin provides a user programming undervoltage

lockout. This is typically used to provide undervoltage

lockout based on VIN. The gate drivers are disabled when

UVLO is below the 1.24V UVLO threshold. An external

resistive divider between the input supply and ground is

used to set the turn-on voltage.

The bias current on this pin depends on the pin volt-

age and UVLO state. The change provides the user with

adjustable UVLO hysteresis. When the pin rises above

the UVLO threshold a small current is sourced out of the

pin, increasing the voltage on the pin. As the pin voltage

drops below this threshold, the current is stopped, further

dropping the voltage on UVLO. In this manner, hysteresis

is produced.

Referring to Figure 13, the voltage hysteresis at VIN is

equal to the change in bias current times RA. The design

procedure is to select the desired VIN referred voltage

hysteresis, VUVHYS. Then:

RA =

VUVHYS

IUVLO

where:

IUVLO = IUVLOL – IUVLOH is approximately 3.4µA

RB is then selected with the desired turn-on voltage:

RB =

VIN(ON)

VUVLO

– 1













APPLICATIONS INFORMATION

VIN

LTC4278

(13a) UV Turning On

UVLO

IUVLO

VIN

LTC4278

(13b) UV Turning Off

(13c) UV Filtering

UVLO

VIN

RA2

RA1

CUVLO

4278 F13

IUVLO

Figure 13. UVLO Pin Function and Recommended Filtering

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