Sensors

Freescale Semiconductor, Inc.

22

MMA7660FC

SERIAL INTERFACE

Serial-Addressing

Data Line (SDA) and a Serial Clock Line (SCL) to achieve bi-directional communication between master(s) and slave(s). A

master (typically a microcontroller) initiates all data transfers to and from the device, and generates the SCL clock that

synchronizes the data transfer.

Figure 7. 2-Wire Serial Interface Timing Details

The device’s SDA line operates as both an input and an open-drain output. A pull-up resistor, typically 4.7 k

Ω, is required on

SDA. The device’s SCL line operates only as an input. A pull-up resistor, typically 4.7 k

Ω, is required on SCL if there are multiple

masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output.

Each transmission consists of a START condition (Figure 7) sent by a master, followed by MMA7660FC's 7-bit slave address

plus R/W bit, a register address byte, one or more data bytes, and finally a STOP condition.

Figure 8. Start and Stop Conditions

Start and Stop Conditions

Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a

START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with

the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another

transmission.

Bit Transfer

One data bit is transferred during each clock tap. See Figure 9. The data on SDA must remain stable while SCL is high.

Figure 9. Bit Transfer

SCL

SDA

tLOW

tHIGH

tF

tR

tHD STA

tHD DAT

tHD STA

tSU DAT

tSU STA

tBUF

tSU STO

START

CONDITION

STOP

CONDITION

REPEATED START

CONDITION

START

CONDITION

DATA LINE STABLE

DATA VALID

CHANGE OF

DATA ALLOWED

SDA

SCL

START

CONDITION

SDA

SCL

STOP

CONDITION

P

S