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MMA7660FC Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc |
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MMA7660FC Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 35 page ![]() Sensors 15 Freescale Semiconductor, Inc. MMA7660FC $03: Tilt Status (Read only) TILT BaFro[1:0] 00:Unknown condition of front or back 01: Front: Equipment is lying on its front 10: Back: Equipment is lying on its back PoLa[2:0] 000: Unknown condition of up or down or left or right 001: Left: Equipment is in landscape mode to the left 010: Right: Equipment is in landscape mode to the right 101: Down: Equipment standing vertically in inverted orientation 110: Up: Equipment standing vertically in normal orientation Tap 1: Equipment has detected a tap 0: Equipment has not detected a tap Alert 0: Register data is valid 1: The register was read at the same time as MMA7660FC was attempting to update the contents. Re-read the register Shake 0: Equipment is not experiencing shake in one or more of the axes enabled by SHINTX, SHINTY, and SHINTZ 1: Equipment is experiencing shake in one or more of the axes enabled by SHINTX, SHINTY, and SHINTZ Note: When entering active mode from standby mode, if the device is flat (±1g on Z-axis) the value for BaFro will be back (-1g) or front (+1g) but PoLa will be in unknown condition. if the device is being held in an Up/Down/Right/Left position, the PoLa value will be updated with current orientation, but BaFro will be in unknown condition. $04: Sample Rate Status Register (Read only) SRST AMSRS 0: Samples per second specified in AMSR[2:0] is not active 1: Samples per second specified in AMSR[2:0] is active AWSRS 0: Samples per second specified in AWSR[1:0] is not active 1: Samples per second specified in AWSR[1:0] is active $05: Sleep Count Register (Read/Write) SPCNT Writing to the SPCNT (0x05) register resets the internal sleep counter. SC[7:0] Sets the 8-bit maximum count value for the 8-bit internal sleep counter in Auto-Sleep. When the 8-bit internal sleep counter reaches the value set by SC[7:0], MMA7660FC will exit Auto-Sleep and switch to the samples per second specified in AWSR[1:0] of the SR (0x08) register. D7 D6 D5 D4 D3 D2 D1 D0 Shake Alert Tap PoLa[2] PoLa[1] PoLa[0] BaFro[1] BaFro[0] 000000 0 0 D7 D6 D5 D4 D3 D2 D1 D0 00 0000 AWSRS AMSRS 00 0000 00 D7 D6 D5 D4 D3 D2 D1 D0 SC[7]SC[6]SC[5]SC[4]SC[3]SC[2] SC[1]SC[0] 0 000 0000 |
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