MPC8377E datasheet(32/127 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

8.3.2

MII Management AC Electrical Specifications

This table provides the MII management AC timing specifications.

Table 32. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter

Conditions

Symbol

Min

Max

Unit

Supply voltage (3.3 V)

—

LVDD1

3.135

3.465

Output high voltage

IOH = –1.0 mA

LVDD1 = Min

VOH

2.10

LVDD1 +0.3

Output low voltage

IOL = 1.0 mA

LVDD1 = Min

VOL

GND

0.50

Input high voltage

—

VIH

2.00

—

Input low voltage

—

VIL

—0.80

Input high current

LVDD1 = Max

VIN

1 = 2.1 V

IIH

—30

μA

Input low current

LVDD1 = Max

VIN = 0.5 V

IIL

–600

—

μA

Table 33. MII Management AC Timing Specifications

Parameter

Symbol1

Min

Typical

Max

Unit

Note

MDC frequency

fMDC

—2.5

—

MHz

MDC period

tMDC

—

400

—

MDC clock pulse width high

tMDCH

—

MDC to MDIO valid

tMDKHDV

× (tplb_clk × 8)

—

MDC to MDIO delay

tMDKHDX

—

× (tplb_clk × 8)

2, 4

MDIO to MDC setup time

tMDDVKH

5—

—

MDIO to MDC hold time

tMDDXKH

0—

—

MDC rise time (20%–80%)

tMDCR

——

MDC fall time (80%–20%)

tMDCF

——

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX

symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input

signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For

rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed.

3. Guaranteed by design.

4. tplb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM].

MPC8377E Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

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