MPC8377E datasheet(8/127 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

2.1.2

Power Supply Voltage Specification

This table provides recommended operating conditions for the device. Note that the values in this table are

the recommended and tested operating conditions. Proper device operation outside of these conditions is

not guaranteed.

Input voltage

DDR DRAM signals

MVIN

–0.3 to (GVDD + 0.3)

2, 4

DDR DRAM reference

MVREF

–0.3 to (GVDD + 0.3)

2, 4

Three-speed Ethernet signals

LVIN

–0.3 to (LVDD + 0.3)

—

PCI, DUART, CLKIN, system control and power

management, I2C, and JTAG signals

OVIN

–0.3 to (OVDD + 0.3)

3, 4, 5

Local Bus

LBIN

–0.3 to (LBVDD + 0.3)

—

Storage temperature range

TSTG

–55 to 150

°C—

Notes:

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. (M,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

5. Overshoot/undershoot by OVIN on the PCI interface does not comply to the PCI Electrical Specification for 3.3-V operation,

as shown in Figure 2.

6. L[1,2]_

nVDD includes SDAVDD_0, XCOREVDD, and XPADVDD power inputs.

Table 3. Recommended Operating Conditions

Characteristic

Symbol

Recommended

Value

Unit

Note

Core supply voltage

up to 667 MHz

VDD

1.0 ± 50 mV

800 MHz

1.05 ± 50 mV

PLL supply voltage (e300 core, eLBC and

system)

up to 667 MHz

AVDD

1.0 ± 50 mV

1, 2

800 MHz

1.05 ± 50 mV

1, 2

DDR1 and DDR2 DRAM I/O voltage

GVDD

2.5 V ± 125 mV

1.8 V ± 90 mV

Three-speed Ethernet I/O, MII management voltage

LVDD[1,2]

3.3 V ± 165 mV

2.5 V ± 125 mV

V—

PCI, local bus, DUART, system control and power management, I2C, and

JTAG I/O voltage

OVDD

3.3 V ± 165 mV

Local Bus

LBVDD

1.8 V ± 90 mV

2.5 V ± 125 mV

3.3 V ± 165 mV

V—

Table 2. Absolute Maximum Ratings1 (continued)

Characteristic

Symbol

Max Value

Unit

Note

MPC8377E Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc

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