MPC8377E datasheet(48/127 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

tCLK_DELAY + tIH – tSFSKHOX < tSFSCKL+ tDATA_DELAY

Eqn. 5

This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of

tSFSCLKL =20 ns:

tCLK_DELAY + 5 – 0 < 20 + tDATA_DELAY

tCLK_DELAY < 15 + tDATA_DELAY

11.2.1.3

Full-Speed Write Combined Formula

The following equation is the combined formula to calculate the allowed skew range between the

SD_CLK and SD_DAT/CMD signals on the PCB.

tCLK_DELAY + tIH – tSFSKHOX < tSFSCKL + tDATA_DELAY < tSFSCK+ tCLK_DELAY – tISU – tSFSKHOV

Eqn. 6

11.2.2

Full-Speed Input Path (Read)

This figure provides the data and command input timing diagram.

Figure 28. Full Speed Input Path

11.2.2.1

Full-Speed Read Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed combined propagation delay range of the

SD_CLK and SD_DAT/CMD signals on the PCB.

tCLK_DELAY + tDATA_DELAY + tODLY + tSFSIVKH < tSFSCK

Eqn. 7

tCLK_DELAY + tDATA_DELAY < tSFSCK – tODLY – tSFSIVKH – tINT_CLK_DLY

Eqn. 8

tCLK_DELAY

Output from the

SD CLK at

the card pin

SD card pins

tSFSIVKH

tSFSIXKH

Driving

edge

Sampling

edge

tOH

tDATA_DELAY

tODLY

tSFSCK (clock cycle)

(MPC8377E input hold)

SD CLK at the

MPC8377E pin

Input at the

MPC8377E pins

MPC8377E Datasheet(PDF) 48 Page - Freescale Semiconductor, Inc

MPC8377E Datasheet(HTML) 48 Page - Freescale Semiconductor, Inc

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