MPC8569E datasheet(108/127 Pages) FREESCALE

108 / 127 page

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Enhanced Secure Digital Host Controller (eSDHC)

Freescale Semiconductor

108

The following figure shows how the AC timing diagram applies to GPCM in PLL bypass mode. The same principle applies to

UPM and FCM.

Figure 60. GPCM Output Timing Diagram (PLL Bypass Mode)

2.16

Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface of the MPC8569E.

2.16.1

eSDHC DC Electrical Characteristics

The following table provides the DC electrical characteristics for the eSDHC interface of the MPC8569E.

Table 68. eSDHC Interface DC Electrical Characteristics

At recommended operating conditions with OVDD =3.3 V

Characteristic

Symbol

Condition

Min

Max

Unit

Notes

Input high voltage

VIH

—0.625

× OV

—V

Input low voltage

VIL

—

0.25

× OV

Output high voltage

VOH

IOH = –100 μA at

OVDD min

0.75

× OV

—V

—

Output low voltage

VOL

IOL = 100 μA at

OVDD min

—

0.125

× OV

V—

tarcs +tLBKHOV

LCLK

LAD[0:31]

LBCTL

tLBONOT

LCS_B

LGPL2/LOE_B

address

taddr

taoe +tLBKHOV

LWE_B

tawcs +tLBKHOV

tLBONOT

address

taddr

tawe +tLBKHOV

tLBKHOX

trc

toen

read data

write data

twen

twc

write

read

LALE

1 t

addr is programmable and determined by LCRR[EADC] and ORx[EAD].

2 t

arcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. Refer to the MPC8569E reference manual.

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