MPC8569E datasheet(109/127 Pages) FREESCALE

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Enhanced Secure Digital Host Controller (eSDHC)

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

109

2.16.2

eSDHC AC Timing Specifications

The following table provides the eSDHC AC timing specifications as defined in Figure 61 and Figure 62.

Output high voltage

VOH

IOH = –100 μAOVDD –0.2

—

Output low voltage

VOL

IOL = 2 mA

—

0.3

Input/output leakage current

IIN/IOZ

—–10

μA—

Note:

1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.

2. Open drain mode for MMC cards only.

Table 69. eSDHC AC Timing Specifications

At recommended operating conditions with OVDD =3.3 V

Parameter

Symbol1

Min

Max

Unit

Notes

SD_CLK clock frequency:

SD/SDIO full speed/high speed mode

MMC full speed/high speed mode

fSHSCK

25/50

20/52

MHz

2, 4

SD_CLK clock low time—High speed/Full speed mode

tSHSCKL

7/10

—

SD_CLK clock high time—High speed/Full speed mode

tSHSCKH

7/10

—

SD_CLK clock rise and fall times

tSHSCKR/

tSHSCKF

—

4, 5

Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK

tSHSIVKH

3.7

—

3, 4, 6

Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK

tSHSIXKH

2.5

—

4, 6

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

tSHSKHOV

–3

4, 6

Notes:

1. The symbols used for timing specifications follow the pattern t(first three letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC high

speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the

invalid state (X) or output hold time. Note that in general, the clock reference symbol representation is based on five letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high speed

mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52 MHz for a MMC card.

3. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should

not exceed 0.65ns.

4. Ccard

≤10 pF, (1 card) and C

L = CBUS + CHOST +CCARD ≤ 40 pF.

5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

6. The parameter values apply to both full speed and high speed modes.

Table 68. eSDHC Interface DC Electrical Characteristics (continued)

At recommended operating conditions with OVDD =3.3 V

Characteristic

Symbol

Condition

Min

Max

Unit

Notes

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