DAC5674

SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005

14BIT, 400 MSPS, 2y/4y INTERPOLATING CommsDAC

DIGITALTOANALOG CONVERTER

8

FEATURES

− Linear Phase

− 0.05-dB Pass-Band Ripple

− 80-dB Stop-Band Attenuation

− Interpolation Filters Configurable in Either

Low-Pass or High-Pass Mode, Allows For

Selection High-Order Images

Bypass Mode

20 mA

Operation

APPLICATIONS

Channel

− CDMA: W-CDMA, CDMA2000, IS-95

− TDMA: GSM, IS-136, EDGE/UWC-136

Generation

DESCRIPTION

The DAC5674 is a 14-bit resolution, high-speed, digital-to-analog converter (DAC) with integrated

4

× interpolation filter, onboard clock multiplier, and on-chip voltage reference. The device has been designed

for high-speed digital data transmission in wired and wireless communication systems, high-frequency

direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.

The 4

× interpolation filter is implemented as a cascade of two 2× interpolation filters, each of which can be

configured for either low-pass or high-pass response. This enables the user to select one of the higher order

images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting

high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter

architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and

costs.

In 4

× interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at

intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission

in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter

requirements by filtering out the images in the adjacent Nyquist zones.

The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential

clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is

supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock

divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

Excel is a trademark of Microsoft Corporation.

CommsDAC and PowerPAD are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

Copyright

 2005, Texas Instruments Incorporated