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PC34709VKR2 Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

Part # PC34709VKR2
Description  Power Management Integrated Circuit (PMIC) for i.MX50/53 Families
PDF  142 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PC34709VKR2 Datasheet(HTML) 79 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
79
Freescale Semiconductor
34709
Functional Block Description
Touch Screen Pen detection bias can be enabled via the TSPENDETEN bit in the AD0 register. When this bit is enabled and a
pen touch is detected, the TSPENDET bit in the Interrupt Status 0 register is set and the INT pin is asserted - unless the interrupt
is masked. Pen detection is only active when TSEN is low.
The reference for the touch screen (Touch Bias) is TSREF and is powered from VCORE. During touch screen operation, TSREF
is a dedicated regulator. No loads other than the touch screen should be connected here. When the ADC performs non touch
screen conversions, the ADC does not rely on TSREF and the reference is disabled.
The readouts are designed such that the on chip switch resistances are of no influence on the overall readout. The readout
scheme does not account for contact resistances, as present in the touch screen connectors. The touch screen readings will
have to be calibrated by the user or the factory, where one has to point with a stylus to the opposite corners of the screen. When
reading the X-coordinate, the 10-bit ADC reading represents a 10-bit coordinate, with ‘0’ for a coordinate equal to X-, and full
scale ‘1023’ when equal to X+. When reading the Y-coordinate, the 10-bit ADC reading represents a 10-bit coordinate, with ‘0’
for a coordinate equal to Y-, and full scale ‘1023’ when equal to Y+. When reading contact resistance, the 10-bit ADC reading
represents the voltage drop over the contact resistance created by the known current source, multiplied by 2.
The X-coordinate is determined by applying TSREF over the TSX1 and TSX2 pins, while performing a high-impedance reading
on the Y-plate through TSY1. The Y-coordinate is determined by applying TSREF between TSY1 and TSY2, while reading the
TSX1 pin. The contact resistance is measured by applying a known current into the TSY1 pin of the touch screen and through
the TSX2 pin, which is grounded. The voltage difference between the two remaining terminals TSY2 and TSX1 is measured by
the ADC, and equals the voltage across the contact resistance. Measuring the contact resistance helps determine if the touch
screen is touched with a finger or a stylus.
The TSSELx[1:0] allows the application processor to select its own reading sequence. The TSSELx[1:0] determines what is read
during the touch screen reading sequence, as shown in Table 70. The touch screen will always start at TSSEL0 and read up to
and including the channel set by TSSEL at the TSSTOP[2:0] bits. For example when TSSTOP[2:0] = 010, it will request the ADC
to read channels indicated in TSSEL0, TSSEL1, and TSSEL2. When TSSTOP[2:0] = 111, all eight addresses will be read.
The touch screen readings can be repeated, as in the following example readout sequence, to reduce the interrupt rate and to
allow for easier noise rejection. The dummy conversion inserted between the different readings allows the references in the
system to be pre-biased for the change in touch screen plate polarity. It will read out as ‘0’.
A touch screen reading will take precedence over an ADC sequence. If an ADC reading is triggered during a touch screen event,
the ADC sequence will be overwritten by the touch screen data.
The first touch screen conversion can be delayed from 0 (default) to 600
s by programming the TSDLY1[3:0] bits. The
TSDLY2[3:0] controls the delay between each of the touch screen conversions from 0 to 600
s. TSDLY[2:0] sets the delay after
the last address is converted. TSDLY1, 2, and 3 are set to 0 by default.
Table 70. Touch Screen Action Select
TSSELx[1:0]
Signals Sampled
00
Dummy to discharge TSREF cap
01
X - plate
10
Y - plate
11
Contact
Table 71. TSDLYx[3:0]
TSDLYx[3:0]
Delay in uS
0000
0
0001
40
0010
80
0011
120
0100
160
0101
200
0110
240



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