TUSB7320 datasheet(36/115 Pages) TI1

36 / 115 page

TUSB7320, TUSB7340

SLLSE76J – MARCH 2011 – REVISED MAY 2012

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4.15 Subsystem Vendor ID Register

This register, which is used for system and option card identification purposes, may be required for certain

operating systems. This read-only register is a direct reflection of the Subsystem Access register, which is

read/write and is initialized through the EEPROM (if present) or can be written through the Subsystem

Alias Register at PCI Offset D0h.

PCI register offset: 2Ch

Default value: 0000h

Table 4-22. PCI Register 2Ch

Bit

No.

Reset

State

4.16 Subsystem ID Register

This register, which is used for system and option card identification purposes, may be required for certain

operating systems. This read-only register is a direct reflection of the Subsystem Access register, which is

read/write and is initialized through the EEPROM (if present) or can be written through the Subsystem

Alias Register at PCI Offset D0h.

PCI register offset: 2Eh

Default value: 0000h

Table 4-23. PCI Register 2Eh

Bit

No.

Reset

State

4.17 Capabilities Pointer Register

This read-only register provides a pointer into the PCI configuration header where the PCI power

management block resides. Since the PCI power management registers begin at 40h, this register is

hardwired to 40h.

PCI register offset: 34h

Default value: 40h

Table 4-24. PCI Register 34h

Bit No.

Reset State

CLASSIC PCI CONFIGURATION SPACE

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TUSB7320 Datasheet(PDF) 36 Page - Texas Instruments