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XIO2221 Datasheet(PDF) 5 Page - Texas Instruments |
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XIO2221 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 196 page  XIO2221 www.ti.com SCPS216A – JULY 2009 – REVISED FEBRAURY 2010 6.8 Serial-Bus Control and Status Register ............................................................................... 110 7 1394 OHCI PCI Configuration Space ................................................................................... 111 7.1 Vendor ID Register ...................................................................................................... 112 7.2 Device ID Register ....................................................................................................... 112 7.3 Command Register ...................................................................................................... 113 7.4 Status Register ........................................................................................................... 114 7.5 Class Code and Revision ID Registers ............................................................................... 115 7.6 Cache Line Size and Latency Timer Registers ...................................................................... 115 7.7 Header Type and BIST Registers ..................................................................................... 116 7.8 OHCI Base Address Register .......................................................................................... 116 7.9 TI Extension Base Address Register .................................................................................. 117 7.10 CIS Base Address Register ............................................................................................ 117 7.11 CIS Pointer Register ..................................................................................................... 118 7.12 Subsystem Vendor ID and Subsystem ID Registers ................................................................ 118 7.13 Power Management Capabilities Pointer Register .................................................................. 119 7.14 Interrupt Line and Interrupt Pin Registers ............................................................................ 119 7.15 Minimum Grant and Minimum Latency Registers ................................................................... 120 7.16 OHCI Control Register .................................................................................................. 120 7.17 Capability ID and Next Item Pointer Registers ....................................................................... 121 7.18 Power Management Capabilities Register ............................................................................ 121 7.19 Power Management Control and Status Register ................................................................... 122 7.20 Power Management Extension Registers ............................................................................ 122 7.21 PCI Miscellaneous Configuration Register ........................................................................... 122 7.22 Link Enhancement Control Register ................................................................................... 125 7.23 Subsystem Access Register ............................................................................................ 127 8 1394 OHCI Memory-Mapped Register Space ....................................................................... 128 8.1 OHCI Version Register .................................................................................................. 131 8.2 GUID ROM Register ..................................................................................................... 132 8.3 Asynchronous Transmit Retries Register ............................................................................. 133 8.4 CSR Data Register ...................................................................................................... 133 8.5 CSR Compare Register ................................................................................................. 134 8.6 CSR Control Register ................................................................................................... 134 8.7 Configuration ROM Header Register .................................................................................. 135 8.8 Bus Identification Register .............................................................................................. 135 8.9 Bus Options Register .................................................................................................... 136 8.10 GUID High Register ...................................................................................................... 137 8.11 GUID Low Register ...................................................................................................... 137 8.12 Configuration ROM Mapping Register ................................................................................ 138 8.13 Posted Write Address Low Register ................................................................................... 138 8.14 Posted Write Address High Register .................................................................................. 139 8.15 Vendor ID Register ...................................................................................................... 139 8.16 Host Controller Control Register ....................................................................................... 139 8.17 Self-ID Buffer Pointer Register ......................................................................................... 142 8.18 Self-ID Count Register .................................................................................................. 142 8.19 Isochronous Receive Channel Mask High Register ................................................................. 143 8.20 Isochronous Receive Channel Mask Low Register ................................................................. 145 Copyright © 2009–2010, Texas Instruments Incorporated Contents 5 |
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