TLV809K33DBVT datasheet(4/16 Pages) TI1

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VDD

GND

RESET

TLV809

Oscillator

Reference

Voltage

of 1.137 V

Reset

Logic

Timer

(NOM)

1.1 V

RESET

ForV

<1.1VUndefined

BehaviorofRESET Output

TLV809J25, TLV809L30

TLV809K33, TLV809I50

SLVSA03C – JUNE 2010 – REVISED FEBRUARY 2012

www.ti.com

TIMING REQUIREMENTS

At RL = 1 MΩ, CL = 50 pF, TA = +25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Pulse width at VDD

VDD = VIT– + 0.2 V, VDD = VIT– – 0.2 V

µs

SWITCHING CHARACTERISTICS

At RL = 1 MΩ, CL = 50 pF, TA = +25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay time

VDD ≥ VIT– + 0.2 V; see timing diagram

120

200

280

Propagation (delay) time,

tPHL

VDD to RESET delay

VIL = VIT– – 0.2 V, VIH = VIT– + 0.2 V

µs

high-to-low-level output

FUNCTIONAL BLOCK DIAGRAM

TIMING DIAGRAM

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Product Folder Link(s): TLV809J25 TLV809L30 TLV809K33 TLV809I50

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