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TLV4113MDGQREP Datasheet(PDF) 12 Page - Texas Instruments

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Part # TLV4113MDGQREP
Description  HIGH-OUTPUT-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN
PDF  25 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLV4113MDGQREP Datasheet(HTML) 12 Page - Texas Instruments

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APPLICATION INFORMATION
SHUTDOWN FUNCTION
DRIVING A CAPACITIVE LOAD
CLOAD
RF
Input
Output
RG
RNULL
+
−
RL
CL
RF
Input
Output
RG
RNULL
+
−
RL
Snubber
C
(a)
(b)
S0048-03
OFFSET VOLTAGE
V
OO +
V
IO
1 )
R
F
R
G
" IIB) RS 1 )
R
F
R
G
" IIB* RF
+
−
VI
+
RG
RS
RF
IIB−
VO
IIB+
S0094-01
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
Two members of the TLV411x family (TLV4110/3) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to just nano amps
per channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. In order to save
power in shutdown mode, an external pullup resistor is required; therefore, to enable the amplifier, the shutdown
terminal must be pulled high. When the shutdown terminal is left floating, care should be taken to ensure that
parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into
shutdown.
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device's
phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than
1 nF, it is recommended that a resistor be placed in series ®NULL) with the output of the amplifier, as shown in
Figure 27. A maximum value of 20
Ω is recommended for most applications.
Figure 27. Driving a Capacitive Load
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage.
Figure 28. Output Offset Voltage Model
12
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP



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