KMB-001LEVALZ datasheet(27/34 Pages) INTERSIL

27 / 34 page

ISLA214P12

FN7982.2

June 27, 2012

'0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address

0x71.

ADDRESS 0X72: CLOCK_DIVIDE

The ISLA214P12 has a selectable clock divider that can be set to

divide by four, two or one (no division). By default, the tri-level

CLKDIV pin selects the divisor. This functionality can be

overridden and controlled through the SPI, as shown in Table 9.

This register is not changed by a Soft Reset.

ADDRESS 0X73: OUTPUT_MODE_A

The output_mode_A register controls the physical output format

of the data, as well as the logical coding. The ISLA214P12 can

present output data in two physical formats: LVDS (default) or

LVCMOS. Additionally, the drive strength in LVDS mode can be set

high (default,3mA or low (2mA).

Data can be coded in three possible formats: two’s complement

(default), Gray code or offset binary. See Table 11.

This register is not changed by a Soft Reset.

ADDRESS 0X74: OUTPUT_MODE_B

Bit 6 DLL Range

This bit sets the DLL operating range to fast (default) or slow.

Internal clock signals are generated by a delay-locked loop (DLL),

which has a finite operating range. Table 12 shows the allowable

sample rate ranges for the slow and fast settings.

Bit 4 DDR Enable

Set to a ‘1’ to enable DDR.

ADDRESS 0XB6: CALIBRATION STATUS

The LSB at address 0xB6 can be read to determine calibration

status. The bit is ‘0’ during calibration and goes to a logic ‘1’

when calibration is complete.This register is unique in that it can

be read after POR at calibration, unlike the other registers on

chip, which can’t be read until calibration is complete.

DEVICE TEST

The ISLA214P12 can produce preset or user defined patterns on

the digital outputs to facilitate in-situ testing. A user can pick

from preset built-in patterns by writing to the output test mode

field [7:4] at 0xC0 or user defined patterns by writing to the user

test mode field [2:0] at 0xC0. The user defined patterns should

be loaded at address space 0xC1 through 0xD0, see the “SPI

Memory Map” on page 29 for more detail.The predefined

patterns are shown in Table 13. The test mode is enabled

asynchronously to the sample clock, therefore several sample

clock cycles may elapse before the data is present on the output

bus.

ADDRESS 0XC0: TEST_IO

Bits 7:4 Output Test Mode

These bits set the test mode according to Table 13. Other

values are reserved.User test patterns loaded at 0xC1 through

0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a

pattern depth value to [2:0] at 0xC0. See the memory map.

Bits 2:0 User Test Mode

The three LSBs in this register determine the test pattern in

combination with registers 0xC1 through 0xD0. Refer to the

SPI Memory Map on page 29.

TABLE 9. CLOCK DIVIDER SELECTION

VALUE

0x72[2:0]

CLOCK DIVIDER

000

Pin Control

001

Divide by 1

010

Divide by 2

100

Divide by 4

other

Not Allowed

TABLE 10. OUTPUT MODE CONTROL

VALUE

0x73[7:5]

OUTPUT MODE

000

LVDS 3mA (Default)

001

LVDS 2mA

100

LVCMOS

TABLE 11. OUTPUT FORMAT CONTROL

VALUE

0x73[2:0]

OUTPUT FORMAT

000

Two’s Complement (Default)

FIGURE 42. PHASE SLIP

ADC Input

Clock (500MHz)

Output Data

Clock (250MHz)

No clock_slip

Output Data

Clock (250MHz)

1 clock_slip

Output Data

Clock (250MHz)

2 clock_slip

2ns

4ns

2ns

010

Gray Code

100

Offset Binary

TABLE 12. DLL RANGES

DLL RANGE

MIN

MAX

UNIT

Slow

100

MSPS

Fast

125

MSPS

TABLE 11. OUTPUT FORMAT CONTROL

VALUE

0x73[2:0]

OUTPUT FORMAT

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