SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L

512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9

SYNCHRONOUS FIRST IN, FIRST OUT MEMORIES

SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993

3

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

D0 − D8

6− 1,

32 − 30

I

Data inputs

EF

14

O

Empty-flag. When memory is empty, EF is low and further data reads are ignored by the device. When EF is

high, the memory is not empty and data reads are allowed. EF is synchronized to RCLK by one flip-flop.

FF

15

O

Full-flag. When memory is full, FF is low and data writes are inhibited. FF is synchronized to WCLK by one

flip-flop.

GND

9

Ground

OE

13

I

Output-enable. Q0 − Q8 are in the high-impedance state when OE is high. Q0 − Q8 are active when OE is low.

PAE

8

O

Programmable almost-empty-flag. PAE is low when the FIFO is almost empty based on the value in its offset

register. The default value for the register is empty + 7. PAE is synchronized to RCLK by one flip-flop.

PAF

7

O

Programmable almost-full-flag. PAF is low when the FIFO is almost full based on the value in its offset register.

The default value for the register is full − 7. PAF is synchronized to WCLK by one flip-flop.

Q0 − Q8

16 − 24

O

Data outputs

RCLK

11

I

Read-clock. A data read is performed by the low-to-high transition of RCLK when REN1 and REN2 are

asserted and EF is high.

REN1,

REN2

10,

11

I

Read-enable. Data is read from the FIFO on a low-to-high transition of RCLK when REN1 and REN2 are low

and EF is high.

RS

29

I

Reset. When RS is set low, the read and write pointers are initialized to the first RAM location and the FIFO

is empty. FF and PAF are set high, and EF and PAE are set low. Each bit in the data output register is set low

by a device reset. The FIFO must be reset after power up before data is written.

VCC

Supply voltage

WCLK

27

I

Write-clock. Data is written by the low-to-high transition of WCLK when WEN1 and WEN2/LD are asserted and

FF is high.

WEN1

28

I

Write-enable 1. WEN1 is the only write enable terminal if the device is configured to have programmable flags.

Data is written on a low-to-high transition of WCLK when WEN1 is low and FF is high. If the FIFO is not

configured for programmable flags, data is written on a low-to-high transition of WCLK when WEN1 and WEN2

are asserted and FF is high.

WEN2/LD

26

I

Write-enable 2 / load. This is a dual-purpose input. The FIFO can have either two write enables or

programmable flags. To use WEN2/LD as a WEN2, WEN2/LD must be held high at reset. When WEN2 and

WEN1 are asserted and FF is high, a low-to-high transition of WCLK writes data. To use WEN2/LD as the LD

terminal, it must be held low at reset. In this case, LD is asserted low to write or read the programmable offset

registers.