SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L

512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9

SYNCHRONOUS FIRST IN, FIRST OUT MEMORIES

SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993

9

POST OFFICE BOX 655303

POST OFFICE BOX 1443

RCLK

tw(CLKH)

No Operation

tc

tw(CLKL)

REN1, REN2

EF

WCLK

tsk1 (see Note A)

WEN2

WEN1

OE

th(EN)

tsu(EN)

tpd(R-EF)

tpd(R-EF)

Valid Data

Q0 − Q8

ta

tpd(OE-Q)

ten

tdis

NOTE A: tsk1 is the minimum time between a rising WCLK edge and a subsequent rising RCLK edge for EF to change logic levels during the

current clock cycle. If the time between the rising edge of WCLK and the subsequent rising edge of RCLK is less than tsk1, then EF may

not change its logic level until the next RCLK rising edge.

Figure 4. Read-Cycle Timing