SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L

512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9

SYNCHRONOUS FIRST IN, FIRST OUT MEMORIES

SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993

13

POST OFFICE BOX 655303

POST OFFICE BOX 1443

tw(CLKH)

tw(CLKL)

REN1,

REN2

WCLK

WEN2

(if applicable)

WEN1

PAF

tsu(EN)

RCLK

tpd(W-AF)

See Note D

th(EN)

[Full − (m + 1)] Words in FIFO

(see Note A)

(Full − m) Words in FIFO

(see Note B)

tpd(W-AF)

tsk2

tsu(EN)

th(EN)

NOTES: A. PAF offset = m

B. (512 − m) words for SN74ACT72211L, (1024 − m) words for SN74ACT72221L, (2048 − m) words for SN74ACT72231L, (4096 − m)

words for SN74ACT72241L

C. tsk2 is the minimum time between a rising RCLK edge and the subsequent rising WCLK edge for PAF to change its logic level during

that clock cycle. If the time between the rising edge of RCLK and the subsequent rising edge of WCLK is less than tsk2, then PAF

may not change its logic level until the next WCLK rising edge.

D. If a write is performed on this rising edge of the write clock, there will be [Full − (m − 1)] words in the FIFO when PAF goes low.

Figure 8. Programmable Almost-Full Flag Timing