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SPC560D40L1 Datasheet(PDF) 65 Page - STMicroelectronics

Part # SPC560D40L1
Description  32-bit MCU family built on the Power Architecture® for automotive body electronics applications
PDF  82 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC560D40L1 Datasheet(HTML) 65 Page - STMicroelectronics

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SPC560D30x, SPC560D40x
Electrical characteristics
Doc ID 16315 Rev 5
65/82
4.18
On-chip peripherals
4.18.1
Current consumption
INLX
CC T
Absolute Integral non-
linearity-extended
channels
No overload
—1.5
5
LSB
DNL
CC T
Absolute Differential
non-linearity
No overload
—0.5
1
LSB
EO
CC T Absolute Offset error
—
—2
—
LSB
EG
CC T Absolute Gain error
—
—2
—
LSB
TUEP(7) CC
P Total unadjusted error
for precise channels,
input only pins
Without current injection
–6
6
LSB
T
With current injection
–8
8
TUEX(7) CC
T Total unadjusted error
for extended channel
Without current injection
–10
10
LSB
T
With current injection
–12
12
1.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2.
Analog and digital VSS must be common (to be tied together externally).
3.
VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion
will be clamped respectively to 0x000 or 0xFFF.
4.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal
divider by 2.
5.
During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the
sampling time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock
tS depend on programming.
6.
This parameter does not include the sampling time tS, but only the time for determining the digital result and the time to load
the result’s register with the conversion result.
7.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
Table 42.
ADC conversion characteristics (continued)
Symbol
C
Parameter
Conditions(1)
Value
Unit
Min
Typ
Max
Table 43.
On-chip peripherals current consumption(1)
Symbol
C
Parameter
Conditions
Typical value(2) Unit
IDD_BV(CAN)
CC T
CAN (FlexCAN) supply
current on VDD_BV
500 Kbyte/s Total (static + dynamic)
consumption:
– FlexCAN in loop-back
mode
– XTAL at 8 MHz used as
CAN engine clock source
– Message sending period
is 580 µs
8 * fperiph + 85
µA
125 Kbyte/s
8 * fperiph + 27
µA



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