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SPC560D40L1 Datasheet(PDF) 30 Page - STMicroelectronics |
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SPC560D40L1 Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 82 page ![]() Electrical characteristics SPC560D30x, SPC560D40x 30/82 Doc ID 16315 Rev 5 Note: SRAM data retention is guaranteed with VDD_LV not below 1.08 V. Table 13. Recommended operating conditions (5.0 V) Symbol C Parameter Conditions Value Unit Min Max VSS S R — Digital ground on VSS_HV pins — 0 0 V VDD (1) S R — Voltage on VDD_HV pins with respect to ground (VSS) —4.5 5.5 V Voltage drop(2) 3.0 5.5 VSS_LV (3) S R — Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) —VSS − 0.1 VSS +0.1 V VDD_BV (4) S R — Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) —4.5 5.5 V Voltage drop(2) 3.0 5.5 Relative to VDD VDD − 0.1 VDD +0.1 VSS_ADC S R — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS —VSS − 0.1 VSS +0.1 V VDD_ADC (5) S R — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) —4.5 5.5 V Voltage drop(2) 3.0 5.5 Relative to VDD VDD − 0.1 VDD +0.1 VIN S R — Voltage on any GPIO pin with respect to ground (VSS) —VSS − 0.1 — V Relative to VDD —VDD +0.1 IINJPAD S R — Injected input current on any pin during overload condition — −55 mA IINJSUM S R — Absolute sum of all injected input currents during overload condition — −50 50 TVDD S R —VDD slope to ensure correct power up (6) — — 0.25 V/µs TA S R — Ambient temperature under bias fCPU ≤ 48 MHz −40 125 °C TJ S R — Junction temperature under bias — −40 150 1. 100 nF capacitance needs to be provided between each VDD/VSS pair. 2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 4. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 5. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. 6. Guaranteed by device validation |
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