PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Features

Freescale Semiconductor

14

— Zero to eight bytes data length

— Programmable bit rate as fast as 1 Mb/sec

— Content-related addressing

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Each MB configurable as receive (Rx) or transmit (Tx), all supporting standard and extended

messages

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Individual Rx mask registers per message buffer

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Includes 1056 bytes of RAM used for message buffer storage

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Includes 256 bytes of RAM used for individual Rx mask registers

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Full featured Rx FIFO with storage capacity for six frames and internal pointer handling

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Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either eight extended,

16 standard, or 32 partial (8 bits) IDs, with individual masking capability

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Selectable backwards compatibility with previous CAN version

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Programmable clock source to the CAN protocol interface, either bus clock or crystal oscillator

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Unused message buffer and Rx mask register space can be used as general-purpose RAM space

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Listen-only mode capability

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Programmable loop-back mode supporting self-test operation

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Programmable transmission priority scheme: lowest ID, lowest buffer number or local priority on

individual Tx message buffers.

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Hardware cancellation on Tx message buffers.

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Time stamp based on 16-bit free-running timer

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Global network time, synchronized by a specific message

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Maskable interrupts

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Independent of the transmission medium (an external transceiver is assumed)

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Short latency time due to an arbitration scheme for high-priority messages

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Low-power modes, with programmable wake-up on bus activity

2.5.14

Enhanced direct memory access controller (eDMA2)

The following summarizes the PXR40’s implementation of the eDMA2 controller:

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Second-generation modules capable of performing complex data movements via 64 programmable

channels (eDMA2-A) and 32 programmable channels (eDMA2-B), without intervention from the

host processor

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DMA engine

— Performs source and destination address calculations

— Performs data movement operations

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Includes SRAM-based memory containing the transfer control descriptors (TCD) for the channels.

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All data movement via dual-address transfers: read from source, write to destination

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Programmable source and destination addresses, transfer size, plus support for enhanced

addressing modes