PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Features

Freescale Semiconductor

20

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Individual message buffer reconfiguration supported

— Means provided to safely disable individual message buffers

— Disabled message buffers can be reconfigured

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Two independent receive FIFOs

— One receive FIFO per channel

— As many as 255 entries for each FIFO

— Global frame ID filtering, based on both value/mask filters and range filters

— Global channel ID filtering

— Global message ID filtering for the dynamic segment

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Four configurable slot error counters

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Four dedicated slot status indicators

— Used to observe slots without using receive message buffers

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Measured value indicators for the clock synchronization

— Internal synchronization frame ID and synchronization frame measurement tables can be

copied into the FlexRay memory

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Fractional macroticks are supported for clock correction

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Maskable interrupt sources provided via individual and combined interrupt lines

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One absolute timer

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One timer that can be configured as absolute or relative

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Nexus data trace support

2.5.22

JTAG controller (JTAGC)

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while

remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan

technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC

block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 and

IEEE 1149.7 standards, and supports the following features:

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IEEE 1149.1-2001 Test Access Port (TAP) interface five pins (JCOMP, TDI, TMS, TCK, and

TDO)

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IEEE 1149.7 Serial JTAG Test Access Port interface three pins (JCOMP, TMS, TCK)

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A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP

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A 5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE, ACCESS_AUX_TAP_eTPU,

ACCESS_AUX_TAP_DMAAN3, ACCESS_AUX_TAP_DMABN3,

ACCESS_AUX_TAP_FLEXRAY

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Three test data registers: a bypass register, a boundary scan register, and a device identification

register. The size of the boundary scan register is parameterized to support a variety of boundary

scan chain lengths.