AD5142ABCPZ100-RL7 datasheet(26/32 Pages) AD

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AD5122A/AD5142A

Data Sheet

Rev. A | Page 26 of 32

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices, Inc., has

patented the RDAC segmentation architecture for all the digital

potentiometers. In particular, the AD5122A/AD5142A employ

a three-stage segmentation approach, as shown in Figure 37.

The AD5122A/AD5142A wiper switch is designed with the

transmission gate CMOS topology and with the gate voltage

derived from VDD and VSS.

7-BIT/8-BIT

ADDRESS

DECODER

STS

SBS

Figure 37. AD5122A/AD5142A Simplified RDAC Circuit

Top Scale/Bottom Scale Architecture

In addition, the AD5122A/AD5142A include new positions to

reduce the resistance between terminals. These positions are

called bottom scale and top scale. At bottom scale, the typical

wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ).

At top scale, the resistance between Terminal A and Terminal W

is decreased by 1 LSB, and the total resistance is reduced to

60 Ω (RAB = 100 kΩ).

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation—±8% Resistor Tolerance

The AD5122A/AD5142A operate in rheostat mode when only two

terminals are used as a variable resistor. The unused terminal can

be floating, or it can be tied to Terminal W, as shown in Figure 38.

Figure 38. Rheostat Mode Configuration

The nominal resistance between Terminal A and Terminal B,

RAB, is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by

the wiper terminal. The 7-bit/8-bit data in the RDAC latch is

decoded to select one of the 128/256 possible wiper settings. The

general equations for determining the digitally programmed

output resistance between Terminal W and Terminal B are

AD5122A:







128

)

(

From 0x00 to 0x7F

(1)

AD5142A:







256

)

(

From 0x00 to 0xFF

(2)

where:

D is the decimal equivalent of the binary code in the 7-bit/8-bit

RDAC register.

RAB is the end-to-end resistance.

RW is the wiper resistance.

In potentiometer mode, similar to the mechanical potentiometer,

the resistance between Terminal W and Terminal A also

produces a digitally controlled complementary resistance, RWA.

RWA also gives a maximum of 8% absolute resistance error. RWA

starts at the maximum resistance value and decreases as the data

loaded into the latch increases. The general equations for this

operation are

AD5122A:









128

)

(

From 0x00 to 0x7F

(3)

AD5142A:









256

)

(

From 0x00 to 0xFF (4)

where:

D is the decimal equivalent of the binary code in the 7-bit/8-bit

RDAC register.

RAB is the end-to-end resistance.

RW is the wiper resistance.

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