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PCAL9535APW Datasheet(PDF) 4 Page - NXP Semiconductors |
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PCAL9535APW Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 46 page ![]() PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 28 September 2012 4 of 46 NXP Semiconductors PCAL9535A Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 2. Pin configuration for TSSOP24 Fig 3. Pin configuration for HWQFN24 PCAL9535APW INT VDD A1 SDA A2 SCL P0_0 A0 P0_1 P1_7 P0_2 P1_6 P0_3 P1_5 P0_4 P1_4 P0_5 P1_3 P0_6 P1_2 P0_7 P1_1 VSS P1_0 002aah426 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aah427 PCAL9535AHF Transparent top view P1_3 P0_4 P0_5 P1_4 P0_3 P1_5 P0_2 P1_6 P0_1 P1_7 P0_0 A0 terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 Table 3. Pin description Symbol Pin Type Description TSSOP24 HWQFN24 INT 1 22 O Interrupt output. Connect to VDD through a pull-up resistor. A1 2 23 I Address input 1. Connect directly to VDD or VSS. A2 3 24 I Address input 2. Connect directly to VDD or VSS. P0_0[2] 4 1 I/O Port 0 input/output 0. P0_1[2] 5 2 I/O Port 0 input/output 1. P0_2[2] 6 3 I/O Port 0 input/output 2. P0_3[2] 7 4 I/O Port 0 input/output 3. P0_4[2] 8 5 I/O Port 0 input/output 4. P0_5[2] 9 6 I/O Port 0 input/output 5. P0_6[2] 10 7 I/O Port 0 input/output 6. P0_7[2] 11 8 I/O Port 0 input/output 7. VSS 12 9[1] power Ground. P1_0[3] 13 10 I/O Port 1 input/output 0. P1_1[3] 14 11 I/O Port 1 input/output 1. P1_2[3] 15 12 I/O Port 1 input/output 2. P1_3[3] 16 13 I/O Port 1 input/output 3. P1_4[3] 17 14 I/O Port 1 input/output 4. P1_5[3] 18 15 I/O Port 1 input/output 5. P1_6[3] 19 16 I/O Port 1 input/output 6. |
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