AD7652 datasheet(12/23 Pages) AD

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PRELIMINARY TECHNICAL DATA

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AD7667

CIRCUIT INFORMATION

The AD7667 is a very fast, low power, single supply, pre-

cise 16-bit analog-to-digital converter (ADC). The

AD7667 features different modes to optimize performances

according to the applications.

In warp mode, the AD7667 is capable of converting

1,000,000 samples per second (1MSPS).

The AD7667 provides the user with an on-chip track/hold,

successive approximation ADC that does not exhibit any pipe-

line or latency, making it ideal for multiple multiplexed channel

applications.

The AD7667 can be operated from a single 5 V supply and

be interfaced to either 5 V or 3 V digital logic. It is housed

in either a 48-lead LQFP package or a 48-lead LFCSP that

saves space and allows flexible configurations as either serial or

parallel interface. The AD7667 is a pin-to-pin compatible

upgrade of the AD7661/64/66.

CONVERTER OPERATION

The AD7667 is a successive-approximation analog-to-digital

converter based on a charge redistribution DAC. Figure 3 shows

the simplified schematic of the ADC. The capacitive DAC consists

of an array of 16 binary weighted capacitors and an additional

“LSB” capacitor. The comparator’s negative input is connected to a

“dummy” capacitor of the same value as the capacitive DAC

array.

During the acquisition phase, the common terminal of the array

tied to the comparator's positive input is connected to AGND

via SWA. All independent switches are connected to the analog

input IN. Thus, the capacitor array is used as a sampling capaci-

tor and acquires the analog signal on IN input. Similarly, the

“dummy” capacitor acquires the analog signal on INGND input.

When the

CNVST input goes low, a conversion phase is initi-

ated. When the conversion phase begins, SWA and SWB are

opened first. The capacitor array and the “dummy” capacitor are

then disconnected from the inputs and connected to the REF-

GND input. Therefore, the differential voltage between IN and

INGND captured at the end of the acquisition phase is applied

to the comparator inputs, causing the comparator to become

unbalanced. By switching each element of the capacitor array

between REFGND or REF, the comparator input varies by

binary-weighted voltage steps (VREF/2, VREF/4, .. .VREF/65536).

The control logic toggles these switches, starting with the MSB

first, to bring the comparator back into a balanced condition.

After the completion of this process, the control logic generates

the ADC output code and brings BUSY output low.

Modes of Operation

The AD7667 features three modes of operations, Warp, Normal,

and Impulse. Each of these modes is more suitable for specific

applications.

The Warp mode allows the fastest conversion rate up to 1

MSPS. However, in this mode, and this mode only, the full

specified accuracy is guaranteed only when the time between

conversion does not exceed 1 ms. If the time between two con-

secutive conversions is longer than 1 ms, for instance, after

power-up, the first conversion result should be ignored. This

mode makes the AD7667 ideal for applications where both high

accuracy and fast sample rate are required.

The normal mode is the fastest mode (800 kSPS) without any

limitation about the time between conversions. This mode

makes the AD7667 ideal for asynchronous applications such as

data acquisition systems, where both high accuracy and fast

sample rate are required.

The impulse mode, the lowest power dissipation mode, allows

power saving between conversions. When operating at 100 SPS,

for example, it typically consumes only 15 µW. This feature

makes the AD7667 ideal for battery-powered applications.

Transfer Functions

Using the OB/

2C digital input, the AD7667 offers two output

codings: straight binary and two’s complement. The LSB size is

VREF/65536, which is about 38.15 µV. The ideal transfer charac-

teristic for the AD7667 is shown in Figure 4 and Table I.

000...000

000...001

000...010

111...101

111...110

111...111

ANALOG INPUT

VREF › 1.5 LSB

VREF › 1 LSB

1 LSB

0.5 LSB

1 LSB = VREF/65536

Figure 4. ADC Ideal Transfer Function

SWA

COMP

SWB

REF

REFGND

LSB

MSB

32,768C

INGND

16,384C

65,536C

CONTROL

LOGIC

SWITCHES

CONTROL

BUSY

OUTPUT

CODE

CNVST

Figure 3. ADC Simplified Schematic

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