AD7652 datasheet(14/23 Pages) AD

14 / 23 page

REV. PrA

PRELIMINARY TECHNICAL DATA

–14–

AD7667

different from AVDD. In such case, an input buffer with a

short circuit current limitation can be used to protect the

part.

This analog input structure allows the sampling of the

differential signal between IN and INGND. Unlike other

converters, the INGND input is sampled at the same time as

the IN input. By using this differential input, small signals

common to both inputs are rejected, as shown in Figure 7,

which represents the typical CMRR over frequency. For in-

stance, by using INGND to sense a remote signal ground,

difference of ground potentials between the sensor and the

local ADC ground are eliminated.

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Figure 7. Analog Input CMR vs. Frequency

During the acquisition phase, the impedance of the analog

input IN can be modeled as a parallel combination of ca-

pacitor C1 and the network formed by the series connection

of R1 and C2. Capacitor C1 is primarily the pin capacitance.

The resistor R1 is typically 183

and is a lumped compo-

nent made up of some serial resistors and the on resistance of

the switches. The capacitor C2 is typically 60 pF and is mainly

the ADC sampling capacitor. During the conversion phase, where

the switches are opened, the input impedance is limited to C1. The

R1, C2 makes a one-pole low-pass filter that reduces undesir-

able aliasing effect and limits the noise.

When the source impedance of the driving circuit is low,

the AD7667 can be driven directly. Large source imped-

ances will significantly affect the ac performances,

especially the total harmonic distortion. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD degrades

in function of the source impedance and the maximum input

frequency as shown in Figure TBD.

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Figure 8. THD vs. Analog Input Frequency and

Source Resistance

Driver Amplifier Choice

Although the AD7667 is easy to drive, the driver amplifier

needs to meet at least the following requirements:

− The driver amplifier and the AD7667 analog input circuit

must be able together to settle for a full-scale step the capaci-

tor array at a 16-bit level (0.0015%). In the amplifier’s data

sheet, the settling at 0.1% to 0.01% is more commonly speci-

fied. It could significantly differ from the settling time at 16

bit level and it should therefore be verified prior to the

driver selection. The tiny op amp AD8021, which com-

bines ultralow noise and a high-gain bandwidth, meets

this settling time requirement even when used with high

gain up to 13.

− The noise generated by the driver amplifier needs to be

kept as low as possible in order to preserve the SNR and

transition noise performance of the AD7667. The noise

coming from the driver is filtered by the AD7667 analog

input circuit one-pole low-pass filter made by R1 and C2

or the external filter if any is used. The SNR degredation

due to the amplifier is:

f-3dB ( N eN )

784 +

(

)

SNRLOSS = 20 LOG

where

f–3dB is the –3 dB input bandwidth of the AD7667 in MHz

(14.5) or the cutoff frequency of the input filter if

any used.

is the noise gain of the amplifier (1 if in buffer

configuration).

e N

is the equivalent input noise voltage of the op amp

nV/

(Hz)

1/2.

For instance, a driver like the AD8021, with an equivalent

input noise of 2 nV/ Hz and configured as a buffer, thus with

a noise gain of 1, the SNR degrades by only 0.13 dB with the

filter used in figure 5.

− The driver needs to have a THD performance suitable to that

of the AD7667.

The AD8021 meets these requirements and is usually appro-

priate for almost all applications. The AD8021 needs an

external compensation capacitor of 10 pF. This capacitor

should have good linearity as an NPO ceramic or mica type.

The AD8022 could also be used where dual version is needed

and gain of 1 is used.

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