AD8108AST datasheet(3/28 Pages) AD

3 / 28 page

AD8108/AD8109

–3–

REV. 0

TIMING CHARACTERISTICS (Serial)

Limit

Parameter

Symbol

Min

Typ

Max

Units

Serial Data Setup Time

CLK Pulsewidth

100

Serial Data Hold Time

CLK Pulse Separation, Serial Mode

100

CLK to

UPDATE Delay

0ns

UPDATE Pulsewidth

CLK to DATA OUT Valid, Serial Mode

180

Propagation Delay,

UPDATE to Switch On or Off

–

Data Load Time, CLK = 5 MHz, Serial Mode

–

6.4

µs

CLK,

UPDATE Rise and Fall Times

–

100

RESET Time

–

200

LOAD DATA INTO

SERIAL REGISTER

ON FALLING EDGE

DATA IN

CLK

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

OUT7 (D3)

OUT7 (D2)

OUT00 (D0)

TRANSFER DATA FROM SERIAL

LATCHES DURING LOW LEVEL

Figure 1. Timing Diagram, Serial Mode

Table I. Logic Levels

VIH

VIL

VOH

VOL

IIH

IIL

IOH

IOL

RESET, SER/PAR

RESET, SER/PAR RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

DATA OUT

CE, UPDATE

DATA OUT

2.0 V min

0.8 V max

2.7 V min

0.5 V max

µA max

–400

µA min

–400

µA max

3.0 mA min

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