AD9873JS datasheet(22/39 Pages) AD

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AD9873

–22–

Digital 8-bit ADC outputs are multiplexed to one 4-bit bus,

clocked by a frequency (fMCLK) of four times the sampling rate

whereas the 10- and 12-bit ADCs are multiplexed together

to one 12-bit bus clocked by fMCLK, which is two times their

sampling frequency.

CLOCK AND OSCILLATOR CIRCUITRY

The AD9873’s internal oscillator generates all sampling clocks

from a simple, low-cost, series resonance, fundamental frequency

quartz crystal. Figure 2 shows how the quartz crystal is connected

between OSC IN (Pin 61) and XTAL (Pin 60) with parallel

resonant load capacitors as specified by the crystal manufacturer.

The internal oscillator circuitry can also be overdriven by a TTL

level clock applied to OSC IN with XTAL left unconnected.

fOSC IN = fMCLK

× N/M

An internal phase locked loop (PLL) generates the DAC sampling

frequency fSYSCLK by multiplying OSC IN frequency M times

(register address 00h). The MCLK signal (Pin 23) fMCLK is

derived by dividing this PLL output frequency with the interpo-

lation rate N of the CIC filter stages (register address 01h).

fSYSCLK = fOSC IN

× M

fMCLK = fOSC IN

× M/N

An external PLL loop filter (Pin 57) consisting of a series resistor

and ceramic capacitor (Figure 15, R1 = 1.3 k

Ω, C12 = 0.01 µF) is

required for stability of the PLL. Also, a shield surrounding these

components is recommended to minimize external noise coupling

into the PLL’s voltage controlled oscillator input (guard trace

connected to AVDD PLL).

Figure 1 shows that ADCs are either directly sampled by a low-

jitter clock at OSC IN or by a clock that is derived from the PLL

output. Operating modes can be selected in register address 08.

Sampling the ADCs directly with the OSC IN clock requires

MCLK to be programmed to be twice the OSC IN frequency.

PIN 1

IDENTIFIER

TOP VIEW

(Pins Down)

AGND IQ

I IN+

I IN–

AGND IQ

REFT8

REFB8

AGND IQ

AVDD IQ

DRVDD

REF CLK

DRGND

DGND SO

SDELTA0

SDELTA1

DVDD SD

CA ENABLE

CA DATA

CA CLK

DVDD OSC

OS IN

XTAL

DGND OSC

AGND PLL

PLL FILTER

AVDD PLL

DVDD PLL

DGND PLL

AVDD Tx

Tx+

Tx–

DRGND

DRVDD

(MSB) IF(11)

IF(10)

IF(9)

IF(8)

IF(7)

IF(6)

IF(5)

IF(4)

IF(3)

IF(2)

IF(1)

IF(0)

(MSB) Rx IQ(3)

Rx IQ(2)

Rx IQ(1)

Rx IQ(0)

Rx SYNC

DRGND

DRVDD

MLCK

DVDD

DGND

Tx SYNC

(MSB) Tx IQ(5)

Tx IQ(4)

Tx IQ(3)

Tx IQ(2)

AD9873

AVDD

0.1 F

CP2

10 F

0.1 F

CP1

10 F

0.1 F

C10

20pF

C11

20pF

1.3k

CP3

10 F

C12

0.01 F

GUARD TRACE

C13

0.1 F

RSET

10k

Figure 2. Basic Connections Diagram

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