AD9873JS datasheet(23/39 Pages) AD

23 / 39 page

REV. 0

AD9873

–23–

PROGRAMMABLE CLOCK OUTPUT REF CLK

The AD9873 provides a frequency programmable clock output

REF CLK (Pin 71). MCLK (fMCLK) and the master clock divider

ratio R stored in register address 01h determine its frequency:

fREF CLK = fMCLK/R

SIGMA-DELTA OUTPUTS

The AD9873 contains two independent sigma-delta outputs

that when low-pass filtered generate level programmable DC

voltages of:

VSD = (Sigma-Delta Code)/4096)(VLOGIC1) +VLOGIC0

(Influenced by CMOS logic output levels.)

tMCLK

000h

001h

002h

800h

FFFh

tMCLK

4096

tMCLK

4096

tMCLK

Figure 3. Sigma-Delta Output Signals

In cable modem set-top box applications the outputs can be used

to control external variable gain amplifiers and RF tuners. A

simple single-pole R-C low-pass filter provides sufficient filtering

(see Figure 4).

SIGMA-DELTA 1

SIGMA-DELTA 0

CONTROL

WORD 1

CONTROL

WORD 0

MCLK

DC (0.4 TO

DRVDD-0.6V)

DC (0.4 TO

DRVDD-0.6V)

TYPICAL: R = 50k

C = 0.01 F

f–3dB = 1/(2 RC) = 318Hz

AD9873

Figure 4. Sigma-Delta RC Filter

In more demanding applications where additional gain, level-shift

or drive capability is required, a first or second order active filter

might be considered for each sigma-delta output (see Figure 5).

SIGMA-DELTA

VDC = (VSD /2 + VOFFSETREF) (1 + R/R1)

GAIN = (1 + R/R1)/ 2

VOFFSET = VOFFSETREF (1 + R/R1)

TYPICAL: R = 50k

C = 0.01 F

f–3dB = 1/(2 RC) = 318Hz

AD9873

VOFFSETREF

OP250

Figure 5. Sigma-Delta Active Filter With Gain and Offset

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9873 serial port is a flexible, synchronous serial communi-

cations port allowing easy interface to many industry standard

microcontrollers and microprocessors. The serial I/O is com-

patible with most synchronous transfer formats, including both the

Motorola SPI and Intel SSR protocols. The interface allows read/

write access to all registers that configure the AD9873. Single

or multiple byte transfers are supported as well as MSB first or

LSB first transfer formats. The AD9873’s serial interface port can

be configured as a single pin I/O (SDIO) or two unidirectional pins

for in/out (SDIO/SDO).

General Operation of the Serial Interface

There are two phases to a communication cycle with the AD9873.

Phase 1 is the instruction cycle, which is the writing of an instruc-

tion byte into the AD9873, coincident with the first eight SCLK

rising edges. The instruction byte provides the AD9873 serial port

controller with information regarding the data transfer cycle, which

is Phase 2 of the communication cycle. The Phase 1 instruction

byte defines whether the upcoming data transfer is read or write,

the number of bytes in the data transfer and the starting register

address for the first byte of the data transfer. The first eight SCLK

rising edges of each communication cycle are used to write the

instruction byte into the AD9873.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9873 and

the system controller. Phase 2 of the communication cycle is

a transfer of 1, 2, 3, or 4 data bytes as determined by the

instruction byte. Normally, using one multibyte transfer is

the preferred method. However, single byte data transfers are

useful to reduce CPU overhead when register access requires

one byte only. Registers change immediately upon writing to the

last bit of each transfer byte.

Instruction Byte

The instruction byte contains the following information as shown

in Table II:

Table II. Instruction Byte Information

R/W

MSB

LSB

R/W, Bit 7 of the instruction byte, determines whether a read or

a write data transfer will occur after the instruction byte write.

Logic high indicates read operation. Logic zero indicates a write

operation. N1, N0, Bits 6 and 5 of the instruction byte, determine

the number of bytes to be transferred during the data transfer

cycle. The bit decodes are shown in the Table III.

Table III. Decode Bits

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0, of the instruction byte,

determine which register is accessed during the data transfer

portion of the communications cycle. For multibyte transfers,

this address is the starting byte address. The remaining register

addresses are generated by the AD9873.

AD9873JS Datasheet(PDF) 23 Page - Analog Devices

AD9873JS Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Datasheet Download

Link URL