AD9873JS datasheet(31/39 Pages) AD

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REV. 0

AD9873

–31–

lower the ac load impedance. The value of this capacitance will

depend on the source resistance and the required signal band-

width. In systems that must use dc coupling, use an op amp to

comply with the input requirements of the AD9873.

Op Amp Selection Guide

Op amp selection for the AD9873 is highly application-dependent.

In general, the performance requirements of any given application

can be characterized by either time domain or frequency domain

constraints. In either case, one should carefully select an op amp

that preserves the performance of the ADC. This task becomes

challenging when one considers the AD9873’s high-performance

capabilities, coupled with other system-level requirements such

as power consumption and cost. The ability to select the optimal

op amp may be further complicated either by limited power sup-

ply availability and/or limited acceptable supplies for a desired

op amp. Newer high-performance op amps typically have input

and output range limitations in accordance with their lower supply

voltages. As a result, some op amps will be more appropriate in

systems where ac-coupling is allowed. When dc-coupling is

required, op amps’ headroom constraints (such as rail-to-rail op

amps) or ones where larger supplies can be used, should be

considered. Analog Devices offers differential output operational

amplifiers like the AD8131 or AD8132. They can be used for

differential or single-ended-to-differential signal conditioning with

8-bit performance to directly drive ADC inputs. The AD8138

is a higher performance version of the AD8132. It provides

12-bit performance and allows different gain settings. Please

contact the factory or local sales office for updates on Analog

Devices’ latest amplifier product offerings.

ADC Differential Inputs

The AD9873 uses 1 V p-p input span for the 8-bit ADC inputs

and 2 V p-p for the 10- and 12-bit ADCs. Since not all applica-

tions have a signal preconditioned for differential operation, there

is often a need to perform a single-ended-to-differential conver-

sion. In systems that do not need a dc input, an RF transformer

with a center tap is the best method to generate differential inputs

beyond 20 MHz for the AD9873. This provides all the benefits

of operating the ADC in the differential mode without con-

tributing additional noise or distortion. An RF transformer also

has the added benefit of providing electrical isolation between

the signal source and the ADC. An improvement in THD and

SFDR performance can be realized by operating the AD9873

in differential mode. The performance enhancement between

the differential and single-ended mode is most considerable as

the input frequency approaches and goes beyond the Nyquist

frequency (i.e., fIN > FS/2).

AINP

AINN

SINGLE-ENDED

ANALOG INPUT

AD9873

AD8131

Figure 21. Single-Ended-to-Differential Input Drive

The AD8131 provides a convenient method of converting a single-

ended signal to a differential signal. This is an ideal method for

generating a direct coupled signal to the AD9873. The AD8131

will accept a signal swinging below 0 V and shift it to an externally

provided common-mode voltage. The AD8131 configuration

is shown in Figure 21.

AINP

AINN

AD9873

Figure 22. Transformer-Coupled Input

Figure 22 shows the schematic of a suggested transformer circuit.

Transformers with turns ratios (n2/n1) other than one may be

selected to optimize the performance of a given application. For

example, selecting a transformer with a higher impedance ratio

(e.g., Mini-Circuits T16–6T with an impedance ratio of (z2/z1)

= 16 = (n2/n1)

2) effectively “steps up” the signal amplitude, thus

further reducing the driving requirements of the signal source. In

Figure 22, a resistor, R1, is added between the analog inputs

to match the source impedance R as in the formula R1 4kV =

(z2/z1)R.

ADC Voltage References

The AD9873 has three independent internal references for its

8-bit, 10-bit, and 12-bit ADCs. Both 8-bit ADCs have a 1 V p-p

input and share one internal reference source. The 10-bit and

12-bit ADCs, however, are designed for 2 V p-p input voltages with

each of them having their own internal reference. Figure 15 shows

the proper connections of the reference pins REFT and REFB.

External references may be necessary for systems that require high

accuracy gain matching between ADCs or improvements in tem-

perature drift and noise characteristics. External references REFT

and RFB need to be centered at AVDD/2 with offset voltages

as specified:

REFT-8: AVDDIQ/2 + 0.25 V REFB-8: AVDDIQ/2 – 0.25 V

REFT-10, -12: AVDD/2 + 0.5 V REFB-10, -12: AVDD/2 – 0.5 V

A differential level of 0.5 V between the reference pins results in

a 1 V p-p ADC input level AIN. A differential level of 1 V between

the reference pins results in a 2 V p-p ADC input level AIN.

Internal reference sources can be powered down when exter-

nal references are used (Register Address 02h).

Video Input

For sampling video-type waveforms, such as NTSC and PAL

signals, the Video Input channel provides black level clamping.

Figure 23 shows the circuit configuration for using the video

channel input (Pin 100). An external blocking capacitor is used

with the on-chip video clamp circuit, to level-shift the input

signal to a desired reference level. The clamp circuit automati-

cally senses the most negative portion of the input signal, and

adjusts the voltage across the input capacitor. This forces the

black level of the input signal to be equal to the value programmed

into the clamp level register (register address 07h).

ADC

CLAMP

LEVEL

LPF

DAC

VIDEO INPUT

CLAMP LEVEL + FS/2

CLAMP LEVEL

BUFFER

0.1 F

2 A

OFFSET

AD9873

Figure 23. Video Clamp Circuit Input

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